K=7 FEC with interleaving + LibreSDR hardware support #27
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…n't derail the firmware build
… type cast from std_logic to boolean. Now make will work.
…rary/msk_top_ip.tcl
… is called out for /axi4lite_intf_pkg.vhd
…k.axi4lite_intf_pkg.ALL; --USE work.msk_top_regs_pkg.ALL; USE work.pkg_msk_top_regs.ALL;
…op_regs_pkg in msk_top_csr.vhd
…files list in librar/msk_top_ip.tcl
…e debug registers from sync_detect, and publishing the updated branch
- Updated signal naming: fifo_overflow -> frame_buffer_overflow in msk_top - Added VHDL-2008 conversion to RDL Makefile for XSim compatibility - Converted PeakRDL generated files to VHDL-2008 (context -> use clauses) - Testbench successfully simulates with frame sync locking XSim requires VHDL-2008 syntax while synthesis accepts VHDL-2019. RDL Makefile now auto-converts generated files after generation.
…t using TLAST as a trigger. TLAST already works automatically with the AXIS DMA. It marks frame boundaries and the DMA respects it without needing any special config. SYNC_TRANSFER_START was erroneously set to TRUE, which overrode the FALSE setting in the ADC DMA block in system_bd.tcl. Once this was fixed, rx_buffer_refill() no longer timed out and data is being seen by the processor side application.
… that must be initialized and signals where the initialization can and was removed
…then installed in msk_top.vhd. Compiles clean.
… data to modem. Randomization, FEC, Interleaving all working as intended.
…te. Right before generate byte vs bit interleaver option installed.
…d working for us. added a lot of comments about this to the source code.
…r that. works in encoder-decoder testbench and end-to-end testbench.
…pletion. Don't wait for tready.
…rame completion. Don't wait for tready." because it did not work in simulation. This reverts commit 44356f2.
… tracing through the PRBS mux and determining that the entire TX data path was unused, and then removed the deserializer, the encoder_tdata buses, fifo_tadatoutputs (which gave a no routable loads warning that tipped me off) and tx_data_bit signal. Added do not touch attributes to preserve evertyhing. This may have been the reason we were stalling.
- Add projects/libre/ with HDL project files (LVDS interface, XC7Z020-CLG400) - Add firmware/scripts/libre.mk and libre.its for firmware build - Add firmware/ori/libre/ with device tree and config files for submodules - Add setup_libre.sh script to install files into submodules after clone - Update firmware/Makefile to support TARGET=libre Pin constraint fixes from hz12opensource patch: - gpio_status[5]: Moved from T20 to G14 to avoid conflict Build instructions: cd firmware/ori/libre && ./setup_libre.sh cd ~/pluto_msk/firmware make TARGET=libre XSA_FILE=/path/to/system_top.xsa LibreSDR provides 53,200 LUTs vs PlutoSDR's 17,600 (3x capacity)
…ile was not copying over cleanly and the build was failing.
- Fix projects/libre/Makefile paths to use ../../hdl/projects/scripts/ - Add libre XSA build block to firmware/Makefile Now 'make TARGET=libre' auto-builds HDL like pluto does.
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Major release adding forward error correction and LibreSDR hardware support.
Encoder/Decoder Changes
dont_touchattributes to prevent Vivado optimizationLibreSDR Support (new TARGET=libre)
make TARGET=libreBuild Instructions
PlutoSDR (existing)
make TARGET=pluto
LibreSDR (new)
cd firmware/ori/libre && ./setup_libre.sh
cd ../../ && make TARGET=libre