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7e15c4a
Switch from desyrdl to peakrdl for sysrdl
mwishek Oct 26, 2025
860deae
CDC updates for CSRs and PeakRDL transition complete
mwishek Oct 27, 2025
3cf82bb
Resolve merge/rebase conflicts
mwishek Oct 27, 2025
ca022b9
Add read back of async FIFO read/write pointers
mwishek Oct 27, 2025
4923b1f
Fix fifo pointer read
mwishek Oct 27, 2025
ccd7b74
added the = '1' so implicit type casting from std_logic to boolean wo…
Abraxas3d Oct 27, 2025
5da15eb
added = '1' to rd_status_req_sync2 test in order to gresolve implicit…
Abraxas3d Oct 27, 2025
a0e1f6f
added /rdl/src/axi4lite_intf_pkg.vhd to the IP list in /pluto_msk/lib…
Abraxas3d Oct 27, 2025
b23e0f8
putting read_vhdl pkg_msk_top_regs.vhd up above, and making sure 2008…
Abraxas3d Oct 28, 2025
3558ba2
there was a name mismatch so I changed it to match like this: USE wor…
Abraxas3d Oct 28, 2025
bdac6a3
Remove rdl/vhdl folder and contents, revert USE library to work.msk_t…
mwishek Oct 28, 2025
a56c29b
added reg_utils.vhd to /library/msk_top_ip.tcl build script
Abraxas3d Oct 28, 2025
0550e64
removed desyrdl package from /library/msk_top_ip.tcl build script
Abraxas3d Oct 28, 2025
5266d12
changed path from rdl/vhdl/msk_top_regs/ to rdl/outputs/rtl
Abraxas3d Oct 28, 2025
e3c30b9
cast the wrong spell but fixed it to /rdl/outputs/rtl/msk_top_regs.vhd
Abraxas3d Oct 28, 2025
cfe0a80
vhdl2008 added to reg_utils.vhd to resolve errors
Abraxas3d Oct 28, 2025
d821407
vhdl2008 added to msk_top_regs.vhd. Should be the last one?
Abraxas3d Oct 28, 2025
86943dd
added cdc_resync.vhd pulse_detect.vhd and data_capture.vhd to add ip …
Abraxas3d Oct 28, 2025
dc22efd
Update regmap in README.md
mwishek Oct 29, 2025
e0dd889
rdl: move away from external registers to a write to capture model
mwishek Nov 4, 2025
fce224f
rdl: update descriptions for write-to-capture registers
mwishek Nov 4, 2025
eadbfcb
rdl: update register descriptions, add HTML output
mwishek Nov 6, 2025
a908758
sim: add readback of power register
mwishek Nov 6, 2025
0613fd1
Reset hdl submodule to match main
Abraxas3d Nov 7, 2025
169f9bd
merging edits from main to peakrdl, resolving conflicts to include th…
Abraxas3d Nov 7, 2025
9eb101e
Add XSim testbench support with PeakRDL compatibility
Abraxas3d Nov 8, 2025
6aeaa74
SYNC_TRANSFER_START is asking for a separate external sync signal, no…
Abraxas3d Nov 8, 2025
0cf8b61
rdl: register description improvements
mwishek Nov 8, 2025
a767c1c
rdl: output artifacts
mwishek Nov 8, 2025
5976835
resolved issue number 22 with comments to distinguish between signals…
Abraxas3d Nov 11, 2025
7d7a5f0
Merge branch 'peakrdl' of https://github.com/OpenResearchInstitute/pl…
Abraxas3d Nov 11, 2025
18ed769
Revert frame_sync_detector.vhd - initialization changes inadvertently…
Abraxas3d Nov 12, 2025
7948a30
Remove unnecessary signal initializations and fix missing counter resets
Abraxas3d Nov 12, 2025
ffc877c
Merge initialization cleanup from test-init-removal
Abraxas3d Nov 12, 2025
1c55316
Clean up signal initializations in AXIS components
Abraxas3d Nov 12, 2025
cfd64ea
rdl: add requested rx frame sync status register
mwishek Nov 13, 2025
19c15f1
rdl: update outputs
mwishek Nov 13, 2025
6174fd3
rdl: update frame sync status register descriptions.
mwishek Nov 14, 2025
628ca20
Improved reset of FIFO read and write pointers. Works in sim and hard…
Abraxas3d Nov 15, 2025
7708fd8
encoder and decoder tested in loopback and pass. encoder and decoder …
Abraxas3d Nov 18, 2025
e0ddf29
data now good in loopback - defeated tricky FIFO to encoder timing bug
Abraxas3d Nov 19, 2025
f9b7ab0
new encoder and decoder files added to the list in msk_top_ip.tcl
Abraxas3d Nov 19, 2025
eae5b60
added hard decision convolutional encoder and decoder
Abraxas3d Nov 20, 2025
8ba0705
hard decision Viterbit decoder installed and input data equals output…
Abraxas3d Nov 20, 2025
e4ce3c2
input matches output but firmware build seg faults. Please send help.
Abraxas3d Nov 21, 2025
af474e7
seg fault resolved. needs testing on full test bench on mymelody.
Abraxas3d Nov 23, 2025
dbc5a1f
end to end data corruption resolved. input equals output.
Abraxas3d Nov 25, 2025
184aa7d
works in simulation, comes under LUT limit for PLUTO, but doesn't rou…
Abraxas3d Nov 25, 2025
a563e0a
simulation looks good for byte level interleaver. byte vs bit now opt…
Abraxas3d Nov 25, 2025
2cc8fa5
simulation now working with yet again the count back from tlast metho…
Abraxas3d Nov 25, 2025
247bead
experiment to isolate encoder as source of lab hardware transmitter s…
Abraxas3d Nov 26, 2025
cd5f27c
decoder created a stall with no gaps between frames. this is a fix fo…
Abraxas3d Nov 27, 2025
44356f2
Change the encoder to deassert tvalid unconditionally after frame com…
Abraxas3d Nov 28, 2025
501c991
Revert "Change the encoder to deassert tvalid unconditionally after f…
Abraxas3d Nov 28, 2025
77336cb
Prevent Vivado from optimizing away data paths. I think synthesis was…
Abraxas3d Nov 28, 2025
e2a45a7
transmitter stall resolved. had 134 as loop limit when needed 268.
Abraxas3d Dec 1, 2025
edc5a7b
Add LibreSDR (XC7Z020/AD9363) support
Abraxas3d Dec 1, 2025
91bd716
Improve the LibreSDR build documentation and setup script. The .xsa f…
Abraxas3d Dec 2, 2025
f57ad15
Fix LibreSDR project paths for auto-build
Abraxas3d Dec 2, 2025
391a18a
Fix system_project.tcl path to adi_env.tcl
Abraxas3d Dec 2, 2025
f4a092e
Fix libre XSA path to TARGETlibre/libre.sdk/
Abraxas3d Dec 2, 2025
b41d0d1
Fix HDL build directory: clear TARGET to prevent TARGETlibre/ subdire…
Abraxas3d Dec 2, 2025
0a1cafe
Use env -u TARGET to fully unset TARGET variable for HDL sub-build
Abraxas3d Dec 2, 2025
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4 changes: 3 additions & 1 deletion README.md
Original file line number Diff line number Diff line change
Expand Up @@ -15,7 +15,7 @@ The following ORI library components are used as submodules to this repository:
7. [Exponential Moving Average Filter](https://github.com/OpenResearchInstitute/lowpass_ema)

## Building
In oder to build the FPGA bitstream, you first need to install Vivado. Recommended version is 2022.2. In this documentation and in the `Makefile`, the Vivado installation path is assumed to be `/opt/Xilinx/Vivado`. If it is in another directory, change the path in the steps below (for example, to `/tools/Xilinx/Vivado`) or create a symbolic link in `/opt` pointing to the actual installation directory. For example,
In order to build the FPGA bitstream, you first need to install Vivado. Recommended version is 2022.2. In this documentation and in the `Makefile`, the Vivado installation path is assumed to be `/opt/Xilinx/Vivado`. If it is in another directory, change the path in the steps below (for example, to `/tools/Xilinx/Vivado`) or create a symbolic link in `/opt` pointing to the actual installation directory. For example,
```
sudo ln -s /tools/Xilinx /opt/Xilinx
```
Expand Down Expand Up @@ -130,6 +130,8 @@ sys 39m46.236s
| 0x84 |lowpass_ema_alpha1| Exponential Moving Average Alpha |
| 0x88 |lowpass_ema_alpha2| Exponential Moving Average Alpha |
| 0x8C | rx_power | Receive Power |
| 0x90 |tx_async_fifo_rd_wr_ptr| Tx async FIFO read and write pointers |
| 0x94 |rx_async_fifo_rd_wr_ptr| Rx async FIFO read and write pointers |


See [MSK Top Regs](rdl/msk_top_regs.pdf) for detailed register definitions.
Expand Down
18 changes: 14 additions & 4 deletions docs/msk_math.md
Original file line number Diff line number Diff line change
Expand Up @@ -115,10 +115,12 @@ The four resulting values for the f1 mix are
cos(2𝝿f1t)*cos(2𝝿f1t) = 1/2 [ cos(2𝝿f1t - 2𝝿f1t) + cos(2𝝿f1t + 2𝝿f1t) ]
= 1/2 [ cos(0) + cos(4𝝿f1t) ]
= 1/2 [ 1 + cos(4𝝿f1t)]
= 1/2 + 1/2cos(2𝝿2f1t)

-cos(2𝝿f1t)*cos(2𝝿f1t) = -1/2 [ cos(2𝝿f1t - 2𝝿f1t) + cos(2𝝿f1t + 2𝝿f1t) ]
= -1/2 [ cos(0) + cos(4𝝿f1t) ]
= -1/2 [ 1 + cos(4𝝿f1t)]
= -1/2 - 1/2cos(2𝝿2f1t)

(both the previous results are a DC value and a sinusoid at 2*f1)

Expand Down Expand Up @@ -149,20 +151,28 @@ cos(2𝝿f1t)*sin(2𝝿f1t) = 1/2 [ sin(2𝝿f1t + 2𝝿f1t + theta) - sin(2𝝿
= 1/2 sin(4𝝿f1t + theta)


-cos(2𝝿f1t)*sin(2𝝿f1t) = -1/2 [ sin(2𝝿f1t + 2𝝿f1t) - sin(2𝝿f1t - 2𝝿f1t) ]
= -1/2 [ sin(4𝝿f1t) - sin(0) ]
= -1/2 sin(4𝝿f1t)
-cos(2𝝿f1t)*sin(2𝝿f1t) = -1/2 [ sin(2𝝿f1t + 2𝝿f1t + theta) - sin(2𝝿f1t - 2𝝿f1t + theta) ]
= -1/2 [ sin(2𝝿2f1t + theta) - sin(theta) ]
= -1/2 sin(2𝝿2f1t + theta)

again we only care about the DC component, which when the phases are aligned is 0. If the phases are not aligned the
sin(0) term becomes sin(Δφ) a constant.


cos(2𝝿f1t)*sin(2𝝿f1t) = 1/2 [ sin(2𝝿f2t + 2𝝿f1t) - sin(2𝝿f2t - 2𝝿f1t) ]
= 1/2 [ sin(2𝝿(f2+f1)t) - sin(2𝝿(f2-f1)t) ]
= 1/2 [ sin(2𝝿(f2+f1)t) - sin(2𝝿(f2-f1)t) ]


cos(2𝝿f1t)*sin(2𝝿f1t) = -1/2 [ sin(2𝝿f2t + 2𝝿f1t) - sin(2𝝿f2t - 2𝝿f1t) ]
= -1/2 [ sin(2𝝿(f2+f1)t) - sin(2𝝿(f2-f1)t) ]




error_instant = 1/2 sin(2𝝿2f1t + theta) * sign( 1/2 + 1/2cos(2𝝿2f1t))
= -1/2 sin(2𝝿2f1t + theta) * sign(-1/2 - 1/2cos(2𝝿2f1t))
= 1/2 sin(2𝝿2f1t + theta)

error = SUM_T(1/2 sin(2𝝿2f1t + theta)) = -cos(2𝝿2f1t + theta) + C


15 changes: 11 additions & 4 deletions firmware/Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -44,7 +44,7 @@ ifneq (1, ${PATCH})
endif

TARGET ?= pluto
SUPPORTED_TARGETS:=pluto plutoplus e200
SUPPORTED_TARGETS:=pluto plutoplus e200 libre
#XSA_FILE ?= ori/bitstream/${TARGET}/system_top.xsa

$(warning *** Building target $(TARGET),)
Expand All @@ -54,9 +54,9 @@ include scripts/$(TARGET).mk

ifeq (, $(shell which dfu-suffix))
$(warning "No dfu-utils in PATH consider doing: sudo apt-get install dfu-util")
TARGETS = build/pluto.frm build/boot.frm
TARGETS = build/$(TARGET).frm build/boot.frm
else
TARGETS = build/$(TARGET).dfu build/uboot-env.dfu build/pluto.frm build/boot.dfu build/boot.frm
TARGETS = build/$(TARGET).dfu build/uboot-env.dfu build/$(TARGET).frm build/boot.dfu build/boot.frm
endif

ifeq ($(findstring $(TARGET),$(SUPPORTED_TARGETS)),)
Expand Down Expand Up @@ -175,6 +175,10 @@ ifeq ($(TARGET),e200)
bash -c "source $(VIVADO_SETTINGS) && make -C ../hdl/projects/pluto-ori-e200 && cp ../hdl/projects/pluto-ori-e200/e200.sdk/system_top.xsa $@"
unzip -l $@ | grep -q ps7_init || cp ../hdl/projects/pluto-ori-e200/e200.srcs/sources_1/bd/system/ip/system_sys_ps7_0/ps7_init* build/
endif
ifeq ($(TARGET),libre)
bash -c "source $(VIVADO_SETTINGS) && env -u TARGET make -C ../projects/libre && cp ../projects/libre/libre.sdk/system_top.xsa $@"
unzip -l $@ | grep -q ps7_init || cp ../projects/libre/libre.srcs/sources_1/bd/system/ip/system_sys_ps7_0/ps7_init* build/
endif
#bash -c "source $(VIVADO_SETTINGS) && make -C ../hdl/projects/pluto-ori-plus"
endif

Expand All @@ -199,7 +203,7 @@ else
endif
### MSD update firmware file ###

build/pluto.frm: build/$(TARGET).itb
build/$(TARGET).frm: build/$(TARGET).itb
md5sum $< | cut -d ' ' -f 1 > [email protected]
cat $< [email protected] > $@

Expand Down Expand Up @@ -235,6 +239,9 @@ endif
ifeq ($(TARGET),e200)
cp build/zynq-e200.dtb $(SDIMGDIR)/devicetree.dtb
endif
ifeq ($(TARGET),libre)
cp build/zynq-libre.dtb $(SDIMGDIR)/devicetree.dtb
endif
cp build/uboot-env.txt $(SDIMGDIR)/uEnv.txt
cp build/rootfs.cpio.gz $(SDIMGDIR)/ramdisk.image.gz
mkimage -A arm -T ramdisk -C gzip -d $(SDIMGDIR)/ramdisk.image.gz $(SDIMGDIR)/uramdisk.image.gz
Expand Down
68 changes: 68 additions & 0 deletions firmware/ori/libre/buildroot-configs/zynq_libre_defconfig
Original file line number Diff line number Diff line change
@@ -0,0 +1,68 @@
BR2_arm=y
BR2_cortex_a9=y
BR2_ARM_ENABLE_NEON=y
BR2_ARM_ENABLE_VFP=y
BR2_ARM_FPU_NEON=y
BR2_TOOLCHAIN_EXTERNAL=y
BR2_TOOLCHAIN_EXTERNAL_LINARO_ARM=y
BR2_OPTIMIZE_3=y
BR2_PACKAGE_ETHTOOL=y
BR2_PACKAGE_ETHTOOL_PRETTY_PRINT=y
BR2_PACKAGE_IPERF3=y
BR2_PACKAGE_HTOP=y
BR2_TARGET_GENERIC_HOSTNAME="libre"
BR2_TARGET_GENERIC_ISSUE="Welcome to LibreSDR"
BR2_ROOTFS_DEVICE_CREATION_DYNAMIC_MDEV=y
BR2_TARGET_GENERIC_ROOT_PASSWD="analog"
BR2_TARGET_GENERIC_GETTY_PORT="ttyPS0"
BR2_ROOTFS_POST_BUILD_SCRIPT="board/libre/post-build.sh"
BR2_PACKAGE_ZSTD=y
BR2_PACKAGE_MTD=y
# BR2_PACKAGE_MTD_NANDDUMP is not set
# BR2_PACKAGE_MTD_NANDTEST is not set
# BR2_PACKAGE_MTD_NANDWRITE is not set
# BR2_PACKAGE_MTD_UBIATTACH is not set
# BR2_PACKAGE_MTD_UBICRC32 is not set
# BR2_PACKAGE_MTD_UBIDETACH is not set
# BR2_PACKAGE_MTD_UBIFORMAT is not set
# BR2_PACKAGE_MTD_UBIMKVOL is not set
# BR2_PACKAGE_MTD_UBINFO is not set
# BR2_PACKAGE_MTD_UBINIZE is not set
# BR2_PACKAGE_MTD_UBIRENAME is not set
# BR2_PACKAGE_MTD_UBIRMVOL is not set
# BR2_PACKAGE_MTD_UBIRSVOL is not set
# BR2_PACKAGE_MTD_UBIUPDATEVOL is not set
# BR2_PACKAGE_MTD_UBIBLOCK is not set
BR2_PACKAGE_LINUX_FIRMWARE=y
BR2_PACKAGE_LINUX_FIRMWARE_RALINK_RT61=y
BR2_PACKAGE_LINUX_FIRMWARE_RALINK_RT73=y
BR2_PACKAGE_LINUX_FIRMWARE_RALINK_RT2XX=y
BR2_PACKAGE_LINUX_FIRMWARE_RTL_81XX=y
BR2_PACKAGE_LINUX_FIRMWARE_RTL_87XX=y
BR2_PACKAGE_LINUX_FIRMWARE_RTL_88XX=y
BR2_PACKAGE_INPUT_EVENT_DAEMON=y
BR2_PACKAGE_UBOOT_TOOLS=y
BR2_PACKAGE_ZLIB=y
BR2_PACKAGE_LIBAD9361_IIO=y
BR2_PACKAGE_LIBGPIOD=y
BR2_PACKAGE_LIBGPIOD_TOOLS=y
BR2_PACKAGE_LIBIIO_IIOD_USBD=y
BR2_PACKAGE_LIBIIO_TESTS=y
BR2_PACKAGE_LIBINI=y
BR2_PACKAGE_AVAHI=y
BR2_PACKAGE_AVAHI_DAEMON=y
BR2_PACKAGE_AVAHI_LIBDNSSD_COMPATIBILITY=y
BR2_PACKAGE_DROPBEAR=y
BR2_PACKAGE_DROPBEAR_LOCALOPTIONS_FILE="board/pluto/dropbrear_localoptions.h"
BR2_PACKAGE_IW=y
BR2_PACKAGE_WPA_SUPPLICANT=y
BR2_PACKAGE_WPA_SUPPLICANT_CLI=y
BR2_PACKAGE_WPA_SUPPLICANT_PASSPHRASE=y
BR2_PACKAGE_POLL_SYSFS=y
BR2_PACKAGE_AD936X_REF_CAL=y
BR2_TARGET_ROOTFS_CPIO=y
BR2_TARGET_ROOTFS_CPIO_GZIP=y
BR2_TARGET_ROOTFS_CPIO_UIMAGE=y
BR2_PACKAGE_HOST_DOSFSTOOLS=y
BR2_PACKAGE_HOST_GENIMAGE=y
BR2_PACKAGE_HOST_MTOOLS=y
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