K=7 FEC with interleaving + LibreSDR hardware support#27

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Abraxas3d wants to merge 63 commits intomainfrom

Commits on Oct 27, 2025

Switch from desyrdl to peakrdl for sysrdl
mwishek
committed
CDC updates for CSRs and PeakRDL transition complete
mwishek
committed
Resolve merge/rebase conflicts
mwishek
committed
Add read back of async FIFO read/write pointers
mwishek
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Fix fifo pointer read
mwishek
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added the = '1' so implicit type casting from std_logic to boolean won't derail the firmware build
Abraxas3d
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added = '1' to rd_status_req_sync2 test in order to gresolve implicit type cast from std_logic to boolean. Now make will work.
Abraxas3d
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added /rdl/src/axi4lite_intf_pkg.vhd to the IP list in /pluto_msk/library/msk_top_ip.tcl
Abraxas3d
committed

Commits on Oct 28, 2025

Commits on Oct 29, 2025

Update regmap in README.md
mwishek
committed

Commits on Nov 4, 2025

Commits on Nov 6, 2025

Commits on Nov 7, 2025

Commits on Nov 11, 2025

Commits on Nov 13, 2025

Commits on Nov 14, 2025

rdl: update frame sync status register descriptions.
mwishek
committed

Commits on Nov 15, 2025

Improved reset of FIFO read and write pointers. Works in sim and hardware.
Abraxas3d
committed

Commits on Nov 18, 2025

encoder and decoder tested in loopback and pass. encoder and decoder then installed in msk_top.vhd. Compiles clean.
Abraxas3d
committed

Commits on Nov 19, 2025

Commits on Nov 20, 2025

Commits on Nov 21, 2025

input matches output but firmware build seg faults. Please send help.
Abraxas3d
committed

Commits on Nov 23, 2025

seg fault resolved. needs testing on full test bench on mymelody.
Abraxas3d
committed

Commits on Nov 26, 2025

experiment to isolate encoder as source of lab hardware transmitter stall
Abraxas3d
committed

Commits on Nov 27, 2025

decoder created a stall with no gaps between frames. this is a fix for that. works in encoder-decoder testbench and end-to-end testbench.
Abraxas3d
committed

Commits on Nov 28, 2025

Commits on Dec 1, 2025