Add NpuSyncOp generation to AIEDmaToNpu #1114
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Coverage ReportCreated: 2024-06-04 22:05Click here for information about interpreting this report.
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AndraBisca
requested review from
denolf,
jgmelber,
fifield and
makslevental
as code owners
fifield
changed the title
fifield
requested changes
Jun 5, 2024
Comment on lines
+441
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+458
| for (auto dma : dmas) { | ||
| if (auto infoOp = | ||
| getAllocOpForSymbol(shimDmaAllocOps, dma.getMetadata())) { | ||
| if (infoOp->getChannelDir() == AIE::DMAChannelDir::S2MM) { | ||
| // Found dma op copying results to host | ||
| OpBuilder builder(dma); | ||
| auto col = builder.getI32IntegerAttr(infoOp->getCol()); | ||
| auto row = builder.getI32IntegerAttr(0); | ||
| auto dir = builder.getI32IntegerAttr(0); | ||
| auto chan = builder.getI32IntegerAttr(infoOp->getChannelIndex()); | ||
| auto col_num = builder.getI32IntegerAttr(1); | ||
| auto row_num = builder.getI32IntegerAttr(1); | ||
| builder.setInsertionPoint(returnOp); | ||
| builder.create<AIEX::NpuSyncOp>(dma->getLoc(), col, row, dir, chan, | ||
| col_num, row_num); | ||
| } | ||
| } | ||
| } |
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I don't think we want to unconditionally add a sync to every outgoing memcpy. For example, what if we are collecting N output tiles at the shim and only need to sync at the end? The N-1 extraneous syncs will have a performance penalty vs. the single (manually inserted) sync at the end.
| @@ -59,7 +59,6 @@ def sequence(A, B, C): | |||
| npu_dma_memcpy_nd( | |||
| metadata="in", bd_id=1, mem=A, sizes=[1, K, M, 1], strides=[1, 1, K] | |||
| ) | |||
| npu_sync(column=0, row=0, direction=0, channel=0) | |||
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I'd prefer that the tests keep the sync explicit, but using aiex.npu.dma_wait instead of aiex.npu.sync
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I'd prefer that the tests keep the sync explicit, but using
aiex.npu.dma_waitinstead ofaiex.npu.sync
Should we close this PR in favor of #1791 ? Or is there still a desire to insert the sync/wait automatically?
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Designs that use objectfifos can rely on the
ShimDMAAllocationOpsgenerated by the objectfifo lowering to produce the correspondingNpuSyncOps. Other designs will still require that the sync be added explicitly.This PR works in relation with the MLIR-AIR channel-to-objectfifo lowering to ensure that the
NpuSyncOpsare added at the MIR-AIE level, after the mapping decisions done by the objectififo lowering.