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Change WireBundle::Ctrl to WireBundle::Control. Decouple WireBundle and StrmSwPortType. #2009

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Change WireBundle::Ctrl to WireBundle::Control. Decouple WireBundle and StrmSwPortType. #2009

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5e96167
Change WireBundle::Ctrl to WireBundle::Control
fifield Jan 8, 2025
9282ad8
clang-format
fifield Jan 8, 2025
5458dd5
Update tests
fifield Jan 8, 2025
97dd9a8
clang-format
fifield Jan 8, 2025
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2 changes: 1 addition & 1 deletion include/aie/Dialect/AIE/IR/AIEAttrs.td
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Original file line number Diff line number Diff line change
Expand Up @@ -49,7 +49,7 @@ def EastWire: I32EnumAttrCase<"East", 6>;
def PLIOWire: I32EnumAttrCase<"PLIO", 7>;
def NOCWire: I32EnumAttrCase<"NOC", 8>;
def TraceWire: I32EnumAttrCase<"Trace", 9>;
def ControlWire: I32EnumAttrCase<"Ctrl", 10>;
def ControlWire: I32EnumAttrCase<"Control", 10>;

def WireBundle: I32EnumAttr<"WireBundle", "Bundle of wires",
[
Expand Down
2 changes: 1 addition & 1 deletion include/aie/Targets/AIERT.h
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Original file line number Diff line number Diff line change
Expand Up @@ -77,7 +77,7 @@ static const std::map<xilinx::AIE::WireBundle, StrmSwPortType>
WIRE_BUNDLE_TO_STRM_SW_PORT_TYPE = {
{xilinx::AIE::WireBundle::Core, StrmSwPortType::CORE},
{xilinx::AIE::WireBundle::DMA, StrmSwPortType::DMA},
{xilinx::AIE::WireBundle::Ctrl, StrmSwPortType::CTRL},
{xilinx::AIE::WireBundle::Control, StrmSwPortType::CTRL},
{xilinx::AIE::WireBundle::FIFO, StrmSwPortType::FIFO},
{xilinx::AIE::WireBundle::South, StrmSwPortType::SOUTH},
{xilinx::AIE::WireBundle::West, StrmSwPortType::WEST},
Expand Down
40 changes: 20 additions & 20 deletions lib/Dialect/AIE/IR/AIETargetModel.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -127,7 +127,7 @@ AIE1TargetModel::getNumDestSwitchboxConnections(int col, int row,
return 0;
return 4;
}
case WireBundle::Ctrl:
case WireBundle::Control:
return isShimNOCTile(col, row) ? 1 : 0;
default:
return 0;
Expand Down Expand Up @@ -155,7 +155,7 @@ AIE1TargetModel::getNumDestSwitchboxConnections(int col, int row,
return 0;
return 4;
}
case WireBundle::Ctrl:
case WireBundle::Control:
return 1;
default:
return 0;
Expand Down Expand Up @@ -185,7 +185,7 @@ AIE1TargetModel::getNumSourceSwitchboxConnections(int col, int row,
}
case WireBundle::Trace:
return 1;
case WireBundle::Ctrl:
case WireBundle::Control:
return isShimNOCTile(col, row) ? 1 : 0;
default:
return 0;
Expand Down Expand Up @@ -215,7 +215,7 @@ AIE1TargetModel::getNumSourceSwitchboxConnections(int col, int row,
}
case WireBundle::Trace:
return 2;
case WireBundle::Ctrl:
case WireBundle::Control:
return 1;
default:
return 0;
Expand Down Expand Up @@ -376,7 +376,7 @@ AIE2TargetModel::getNumDestSwitchboxConnections(int col, int row,
return 6;
case WireBundle::South:
return 4;
case WireBundle::Ctrl:
case WireBundle::Control:
return 1;
default:
return 0;
Expand All @@ -400,7 +400,7 @@ AIE2TargetModel::getNumDestSwitchboxConnections(int col, int row,
return 0;
return 4;
}
case WireBundle::Ctrl:
case WireBundle::Control:
return isShimNOCTile(col, row) ? 1 : 0;
default:
return 0;
Expand Down Expand Up @@ -430,7 +430,7 @@ AIE2TargetModel::getNumDestSwitchboxConnections(int col, int row,
return 0;
return 4;
}
case WireBundle::Ctrl:
case WireBundle::Control:
return 1;
default:
return 0;
Expand All @@ -449,7 +449,7 @@ AIE2TargetModel::getNumSourceSwitchboxConnections(int col, int row,
case WireBundle::South:
return 6;
case WireBundle::Trace:
case WireBundle::Ctrl:
case WireBundle::Control:
return 1;
default:
return 0;
Expand All @@ -475,7 +475,7 @@ AIE2TargetModel::getNumSourceSwitchboxConnections(int col, int row,
}
case WireBundle::Trace:
return 1;
case WireBundle::Ctrl:
case WireBundle::Control:
return isShimNOCTile(col, row) ? 1 : 0;
default:
return 0;
Expand Down Expand Up @@ -509,7 +509,7 @@ AIE2TargetModel::getNumSourceSwitchboxConnections(int col, int row,
case WireBundle::Trace:
// Port 0: core trace. Port 1: memory trace.
return 2;
case WireBundle::Ctrl:
case WireBundle::Control:
return 1;
default:
return 0;
Expand Down Expand Up @@ -577,18 +577,18 @@ bool AIE2TargetModel::isLegalTileConnection(int col, int row,
if (srcBundle == WireBundle::DMA) {
if (dstBundle == WireBundle::DMA)
return srcChan == dstChan;
if (isBundleInList(dstBundle, {WireBundle::Ctrl, WireBundle::South,
if (isBundleInList(dstBundle, {WireBundle::Control, WireBundle::South,
WireBundle::North}))
return true;
}
if (srcBundle == WireBundle::Ctrl) {
if (srcBundle == WireBundle::Control) {
if (dstBundle == WireBundle::DMA)
return dstChan == 5;
if (isBundleInList(dstBundle, {WireBundle::South, WireBundle::North}))
return true;
}
if (isBundleInList(srcBundle, {WireBundle::South, WireBundle::North})) {
if (isBundleInList(dstBundle, {WireBundle::DMA, WireBundle::Ctrl}))
if (isBundleInList(dstBundle, {WireBundle::DMA, WireBundle::Control}))
return true;
if (isBundleInList(dstBundle, {WireBundle::South, WireBundle::North}))
return srcChan == dstChan;
Expand All @@ -602,18 +602,18 @@ bool AIE2TargetModel::isLegalTileConnection(int col, int row,
}
// Shimtile
else if (isShimNOCorPLTile(col, row)) {
if (srcBundle == WireBundle::Ctrl)
return dstBundle != WireBundle::Ctrl;
if (srcBundle == WireBundle::Control)
return dstBundle != WireBundle::Control;
if (isBundleInList(srcBundle, {WireBundle::FIFO, WireBundle::South}))
return isBundleInList(dstBundle, {WireBundle::Ctrl, WireBundle::FIFO,
return isBundleInList(dstBundle, {WireBundle::Control, WireBundle::FIFO,
WireBundle::South, WireBundle::West,
WireBundle::North, WireBundle::East});
if (isBundleInList(srcBundle,
{WireBundle::West, WireBundle::North, WireBundle::East}))
return (srcBundle == dstBundle)
? (srcChan == dstChan)
: isBundleInList(dstBundle,
{WireBundle::Ctrl, WireBundle::FIFO,
{WireBundle::Control, WireBundle::FIFO,
WireBundle::South, WireBundle::West,
WireBundle::North, WireBundle::East});
if (srcBundle == WireBundle::Trace) {
Expand All @@ -629,14 +629,14 @@ bool AIE2TargetModel::isLegalTileConnection(int col, int row,
{WireBundle::DMA, WireBundle::FIFO, WireBundle::South,
WireBundle::West, WireBundle::North, WireBundle::East}))
if (isBundleInList(dstBundle,
{WireBundle::Core, WireBundle::DMA, WireBundle::Ctrl,
{WireBundle::Core, WireBundle::DMA, WireBundle::Control,
WireBundle::FIFO, WireBundle::South, WireBundle::West,
WireBundle::North, WireBundle::East}))
return (srcBundle == dstBundle) ? (srcChan == dstChan) : true;
if (srcBundle == WireBundle::Core)
return dstBundle != WireBundle::Core;
if (srcBundle == WireBundle::Ctrl)
return dstBundle != WireBundle::Ctrl && dstBundle != WireBundle::DMA;
if (srcBundle == WireBundle::Control)
return dstBundle != WireBundle::Control && dstBundle != WireBundle::DMA;
if (srcBundle == WireBundle::Trace) {
if (dstBundle == WireBundle::DMA)
return dstChan == 0;
Expand Down
4 changes: 2 additions & 2 deletions lib/Dialect/AIE/Transforms/AIEGenerateColumnControlOverlay.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -221,7 +221,7 @@ struct AIEGenerateColumnControlOverlayPass

generatePacketFlowsForControl(
builder, device, shimTile, AIE::WireBundle::South, tilesOnCol,
AIE::WireBundle::Ctrl, 0, tileIDMap, false);
AIE::WireBundle::Control, 0, tileIDMap, false);
}
if (clRouteShimDmaToTileCTRL) {
// Get all tile ops on column col
Expand All @@ -234,7 +234,7 @@ struct AIEGenerateColumnControlOverlayPass

generatePacketFlowsForControl(
builder, device, shimTile, AIE::WireBundle::DMA, tilesOnCol,
AIE::WireBundle::Ctrl, 0, tileIDMap, true);
AIE::WireBundle::Control, 0, tileIDMap, true);
}
}
}
Expand Down
2 changes: 1 addition & 1 deletion lib/Dialect/AIE/Transforms/AIEPathFinder.cpp
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Expand Up @@ -198,7 +198,7 @@ void Pathfinder::initialize(int maxCol, int maxRow,
WireBundle::Core, WireBundle::DMA, WireBundle::FIFO,
WireBundle::South, WireBundle::West, WireBundle::North,
WireBundle::East, WireBundle::PLIO, WireBundle::NOC,
WireBundle::Trace, WireBundle::Ctrl};
WireBundle::Trace, WireBundle::Control};
for (WireBundle bundle : bundles) {
// get all ports into current switchbox
int channels =
Expand Down
73 changes: 24 additions & 49 deletions lib/Targets/AIETargetXAIEV2.cpp
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Expand Up @@ -27,10 +27,8 @@ using namespace xilinx;
using namespace xilinx::AIE;
using namespace xilinx::AIEX;

namespace xilinx::AIE {

// This string is output at the top of the lowered C++ code.
const char *xaie_cpp_file_header = R"code(
static const char *xaie_cpp_file_header = R"code(
// This file was auto-generated by aiecc.py --aie-generate-xaie.

#ifndef MLIR_AIE_QUIET
Expand Down Expand Up @@ -69,11 +67,23 @@ static std::string tileLockStr(StringRef id, StringRef val) {
return str;
}

// Translate mlir-aie WireBundle enum to string of aie-rt StrmSwPortType enum
static std::string wireBundleToPortType(WireBundle bundle) {
switch (bundle) {
case WireBundle::PLIO:
return "PL";
case WireBundle::Control:
return "CTRL";
default:
return stringifyWireBundle(bundle).upper();
}
}

// FIXME: code bloat. this shouldn't really be a template, but need
// a proper DMA-like interface
// blockMap: A map that gives a unique bd ID assignment for every block.
template <typename OpType>
mlir::LogicalResult generateDMAConfig(OpType memOp, raw_ostream &output,
static mlir::LogicalResult generateDMAConfig(OpType memOp, raw_ostream &output,
const AIETargetModel &targetModel,
DenseMap<Block *, int> blockMap) {
StringRef enable = "XAIE_ENABLE";
Expand Down Expand Up @@ -294,7 +304,7 @@ mlir::LogicalResult generateDMAConfig(OpType memOp, raw_ostream &output,
return success();
}

mlir::LogicalResult AIETranslateToXAIEV2(ModuleOp module, raw_ostream &output) {
mlir::LogicalResult xilinx::AIE::AIETranslateToXAIEV2(ModuleOp module, raw_ostream &output) {
// StringRef ctx = "ctx"; // TODO
StringRef ctx_p = "aie_libxaie_ctx_t* ctx"; // TODO
// StringRef deviceInst = "ctx->DevInst"; // TODO
Expand Down Expand Up @@ -334,6 +344,8 @@ mlir::LogicalResult AIETranslateToXAIEV2(ModuleOp module, raw_ostream &output) {
case AIEArch::AIE2p:
device = AIE2p_device;
break;
default:
return module.emitOpError("Unsupported aie.device");
}
output << " ctx->AieConfigPtr.AieGen = " << device << ";\n";
output << " ctx->AieConfigPtr.BaseAddr = 0x20000000000;\n";
Expand Down Expand Up @@ -429,38 +441,6 @@ mlir::LogicalResult AIETranslateToXAIEV2(ModuleOp module, raw_ostream &output) {
//---------------------------------------------------------------------------
output << "int mlir_aie_configure_dmas(" << ctx_p << ") {\n";

// DMA configuration
// AieRC XAie_DmaDescInit(XAie_DevInst *DevInst, XAie_DmaDesc *DmaDesc,
// XAie_LocType Loc); AieRC XAie_DmaSetLock(XAie_DmaDesc *DmaDesc, XAie_Lock
// Acq, XAie_Lock Rel); AieRC XAie_DmaSetPkt(XAie_DmaDesc *DmaDesc,
// XAie_Packet Pkt); AieRC XAie_DmaSetOutofOrderBdId(XAie_DmaDesc *DmaDesc, u8
// OutofOrderBdId); AieRC XAie_DmaSetDoubleBuffer(XAie_DmaDesc *DmaDesc, u64
// Addr, XAie_Lock Acq, XAie_Lock Rel); AieRC XAie_DmaSetAddrLen(XAie_DmaDesc
// *DmaDesc, u64 Addr, u32 Len); AieRC XAie_DmaSetMultiDimAddr(XAie_DmaDesc
// *DmaDesc, XAie_DmaTensor *Tensor, u64 Addr, u32 Len); AieRC
// XAie_DmaEnableCompression(XAie_DmaDesc *DmaDesc); AieRC
// XAie_DmaSetNextBd(XAie_DmaDesc *DmaDesc, u8 NextBd, u8 EnableNextBd); AieRC
// XAie_DmaEnableBd(XAie_DmaDesc *DmaDesc); AieRC
// XAie_DmaDisableBd(XAie_DmaDesc *DmaDesc); AieRC XAie_DmaSetAxi(XAie_DmaDesc
// *DmaDesc, u8 Smid, u8 BurstLen, u8 Qos,u8 Cache, u8 Secure); AieRC
// XAie_DmaSetInterleaveEnable(XAie_DmaDesc *DmaDesc, u8 DoubleBuff, u8
// IntrleaveCount, u16 IntrleaveCurr); AieRC XAie_DmaWriteBd(XAie_DevInst
// *DevInst, XAie_DmaDesc *DmaDesc, XAie_LocType Loc, u8 BdNum);

// AieRC XAie_DmaChannelResetAll(XAie_DevInst *DevInst, XAie_LocType Loc,
// XAie_DmaChReset Reset); AieRC XAie_DmaChannelReset(XAie_DevInst *DevInst,
// XAie_LocType Loc, u8 ChNum, XAie_DmaDirection Dir, XAie_DmaChReset Reset);
// AieRC XAie_DmaChannelPauseStream(XAie_DevInst *DevInst, XAie_LocType Loc,
// u8 ChNum, XAie_DmaDirection Dir, u8 Pause); AieRC
// XAie_DmaChannelPauseMem(XAie_DevInst *DevInst, XAie_LocType Loc, u8 ChNum
// XAie_DmaDirection Dir, u8 Pause); AieRC XAie_DmaChannelConfig(XAie_DevInst
// *DevInst, XAie_DmaDesc *DmaDesc, XAie_LocType Loc, u8 ChNum,
// XAie_DmaDirection Dir, u8 RepeatCount, u8 EnTokenIssue, u8 ControllerId);
// AieRC XAie_DmaChannelPushBdToQueue(XAie_DevInst *DevInst, XAie_LocType Loc,
// u8 ChNum, XAie_DmaDirection Dir, u8 BdNum); AieRC
// XAie_DmaChannelEnable(XAie_DevInst *DevInst, XAie_LocType Loc, u8 ChNum,
// XAie_DmaDirection Dir); AieRC XAie_DmaChannelDisable(XAie_DevInst *DevInst,
// XAie_LocType Loc, u8 ChNum, XAie_DmaDirection Dir);
for (auto memOp : targetOp.getOps<MemOp>()) {
DenseMap<Block *, int> blockMap;

Expand Down Expand Up @@ -654,9 +634,9 @@ mlir::LogicalResult AIETranslateToXAIEV2(ModuleOp module, raw_ostream &output) {
for (auto connectOp : b.getOps<ConnectOp>())
output << "__mlir_aie_try(XAie_StrmConnCctEnable(" << deviceInstRef
<< ", " << tileLocStr("x", "y") << ", "
<< stringifyWireBundle(connectOp.getSourceBundle()).upper() << ", "
<< wireBundleToPortType(connectOp.getSourceBundle()) << ", "
<< connectOp.sourceIndex() << ", "
<< stringifyWireBundle(connectOp.getDestBundle()).upper() << ", "
<< wireBundleToPortType(connectOp.getDestBundle()) << ", "
<< connectOp.destIndex() << "));\n";

for (auto connectOp : b.getOps<MasterSetOp>()) {
Expand All @@ -672,7 +652,7 @@ mlir::LogicalResult AIETranslateToXAIEV2(ModuleOp module, raw_ostream &output) {

output << "__mlir_aie_try(XAie_StrmPktSwMstrPortEnable(" << deviceInstRef
<< ", " << tileLocStr("x", "y") << ", "
<< stringifyWireBundle(connectOp.getDestBundle()).upper() << ", "
<< wireBundleToPortType(connectOp.getDestBundle()) << ", "
<< connectOp.destIndex() << ", "
<< "/* drop_header */ "
<< (isdma ? "XAIE_SS_PKT_DROP_HEADER"
Expand All @@ -692,13 +672,13 @@ mlir::LogicalResult AIETranslateToXAIEV2(ModuleOp module, raw_ostream &output) {
int msel = amselOp.getMselValue();
output << "__mlir_aie_try(XAie_StrmPktSwSlavePortEnable("
<< deviceInstRef << ", " << tileLocStr("x", "y") << ", "
<< stringifyWireBundle(connectOp.getSourceBundle()).upper()
<< wireBundleToPortType(connectOp.getSourceBundle())
<< ", " << connectOp.sourceIndex() << "));\n";

// TODO Need to better define packet id,type used here
output << "__mlir_aie_try(XAie_StrmPktSwSlaveSlotEnable("
<< deviceInstRef << ", " << tileLocStr("x", "y") << ", "
<< stringifyWireBundle(connectOp.getSourceBundle()).upper()
<< wireBundleToPortType(connectOp.getSourceBundle())
<< ", " << connectOp.sourceIndex() << ", "
<< "/* slot */ " << slot << ", "
<< "/* packet */ " << packetStr(slotOp.valueInt(), /*type*/ 0)
Expand Down Expand Up @@ -744,17 +724,13 @@ mlir::LogicalResult AIETranslateToXAIEV2(ModuleOp module, raw_ostream &output) {
<< "__mlir_aie_try(XAie_EnableAieToShimDmaStrmPort("
<< deviceInstRef << ", " << tileLocStr("x", "y")
<< ", "
// <<
// stringifyWireBundle(connectOp.sourceBundle()).upper()
<< connectOp.sourceIndex() << "));\n";
else if (connectOp.getDestBundle() == WireBundle::North)
// mux
output
<< "__mlir_aie_try(XAie_EnableShimDmaToAieStrmPort("
<< deviceInstRef << ", " << tileLocStr("x", "y")
<< ", "
// <<
// stringifyWireBundle(connectOp.sourceBundle()).upper()
<< connectOp.destIndex() << "));\n";
}

Expand Down Expand Up @@ -784,9 +760,9 @@ mlir::LogicalResult AIETranslateToXAIEV2(ModuleOp module, raw_ostream &output) {
for (auto connectOp : b.getOps<ConnectOp>())
output << "__mlir_aie_try(XAie_StrmConnCctEnable(" << deviceInstRef
<< ", " << tileLocStr(col, 0) << ", "
<< stringifyWireBundle(connectOp.getSourceBundle()).upper() << ", "
<< wireBundleToPortType(connectOp.getSourceBundle()) << ", "
<< connectOp.sourceIndex() << ", "
<< stringifyWireBundle(connectOp.getDestBundle()).upper() << ", "
<< wireBundleToPortType(connectOp.getDestBundle()) << ", "
<< connectOp.destIndex() << "));\n";
}

Expand Down Expand Up @@ -905,4 +881,3 @@ mlir::LogicalResult AIETranslateToXAIEV2(ModuleOp module, raw_ostream &output) {

return success();
}
} // namespace xilinx::AIE
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