Change WireBundle::Ctrl to WireBundle::TileControl. Decouple WireBundle and StrmSwPortType

include/aie/Dialect/AIE/IR/AIEAttrs.td

@@ -49,12 +49,12 @@ def EastWire:   I32EnumAttrCase<"East", 6>;
 def PLIOWire:   I32EnumAttrCase<"PLIO", 7>;
 def NOCWire:    I32EnumAttrCase<"NOC", 8>;
 def TraceWire:  I32EnumAttrCase<"Trace", 9>;
-def ControlWire:  I32EnumAttrCase<"Ctrl", 10>;
+def TileControlWire:  I32EnumAttrCase<"TileControl", 10>;
 
 def WireBundle: I32EnumAttr<"WireBundle", "Bundle of wires",
   [
     CoreWire, DMAWire, FIFOWire, SouthWire, WestWire, NorthWire,
-    EastWire, PLIOWire, NOCWire, TraceWire, ControlWire
+    EastWire, PLIOWire, NOCWire, TraceWire, TileControlWire
   ]> {
 
   let cppNamespace = "xilinx::AIE";

include/aie/Targets/AIERT.h

@@ -77,7 +77,7 @@ static const std::map<xilinx::AIE::WireBundle, StrmSwPortType>
     WIRE_BUNDLE_TO_STRM_SW_PORT_TYPE = {
         {xilinx::AIE::WireBundle::Core, StrmSwPortType::CORE},
         {xilinx::AIE::WireBundle::DMA, StrmSwPortType::DMA},
-        {xilinx::AIE::WireBundle::Ctrl, StrmSwPortType::CTRL},
+        {xilinx::AIE::WireBundle::TileControl, StrmSwPortType::CTRL},
         {xilinx::AIE::WireBundle::FIFO, StrmSwPortType::FIFO},
         {xilinx::AIE::WireBundle::South, StrmSwPortType::SOUTH},
         {xilinx::AIE::WireBundle::West, StrmSwPortType::WEST},

lib/Dialect/AIE/IR/AIETargetModel.cpp

@@ -127,7 +127,7 @@ AIE1TargetModel::getNumDestSwitchboxConnections(int col, int row,
         return 0;
       return 4;
     }
-    case WireBundle::Ctrl:
+    case WireBundle::TileControl:
       return isShimNOCTile(col, row) ? 1 : 0;
     default:
       return 0;
@@ -155,7 +155,7 @@ AIE1TargetModel::getNumDestSwitchboxConnections(int col, int row,
       return 0;
     return 4;
   }
-  case WireBundle::Ctrl:
+  case WireBundle::TileControl:
     return 1;
   default:
     return 0;
@@ -185,7 +185,7 @@ AIE1TargetModel::getNumSourceSwitchboxConnections(int col, int row,
     }
     case WireBundle::Trace:
       return 1;
-    case WireBundle::Ctrl:
+    case WireBundle::TileControl:
       return isShimNOCTile(col, row) ? 1 : 0;
     default:
       return 0;
@@ -215,7 +215,7 @@ AIE1TargetModel::getNumSourceSwitchboxConnections(int col, int row,
   }
   case WireBundle::Trace:
     return 2;
-  case WireBundle::Ctrl:
+  case WireBundle::TileControl:
     return 1;
   default:
     return 0;
@@ -376,7 +376,7 @@ AIE2TargetModel::getNumDestSwitchboxConnections(int col, int row,
       return 6;
     case WireBundle::South:
       return 4;
-    case WireBundle::Ctrl:
+    case WireBundle::TileControl:
       return 1;
     default:
       return 0;
@@ -400,7 +400,7 @@ AIE2TargetModel::getNumDestSwitchboxConnections(int col, int row,
         return 0;
       return 4;
     }
-    case WireBundle::Ctrl:
+    case WireBundle::TileControl:
       return isShimNOCTile(col, row) ? 1 : 0;
     default:
       return 0;
@@ -430,7 +430,7 @@ AIE2TargetModel::getNumDestSwitchboxConnections(int col, int row,
       return 0;
     return 4;
   }
-  case WireBundle::Ctrl:
+  case WireBundle::TileControl:
     return 1;
   default:
     return 0;
@@ -449,7 +449,7 @@ AIE2TargetModel::getNumSourceSwitchboxConnections(int col, int row,
     case WireBundle::South:
       return 6;
     case WireBundle::Trace:
-    case WireBundle::Ctrl:
+    case WireBundle::TileControl:
       return 1;
     default:
       return 0;
@@ -475,7 +475,7 @@ AIE2TargetModel::getNumSourceSwitchboxConnections(int col, int row,
     }
     case WireBundle::Trace:
       return 1;
-    case WireBundle::Ctrl:
+    case WireBundle::TileControl:
       return isShimNOCTile(col, row) ? 1 : 0;
     default:
       return 0;
@@ -509,7 +509,7 @@ AIE2TargetModel::getNumSourceSwitchboxConnections(int col, int row,
   case WireBundle::Trace:
     // Port 0: core trace. Port 1: memory trace.
     return 2;
-  case WireBundle::Ctrl:
+  case WireBundle::TileControl:
     return 1;
   default:
     return 0;
@@ -577,18 +577,18 @@ bool AIE2TargetModel::isLegalTileConnection(int col, int row,
     if (srcBundle == WireBundle::DMA) {
       if (dstBundle == WireBundle::DMA)
         return srcChan == dstChan;
-      if (isBundleInList(dstBundle, {WireBundle::Ctrl, WireBundle::South,
+      if (isBundleInList(dstBundle, {WireBundle::TileControl, WireBundle::South,
                                      WireBundle::North}))
         return true;
     }
-    if (srcBundle == WireBundle::Ctrl) {
+    if (srcBundle == WireBundle::TileControl) {
       if (dstBundle == WireBundle::DMA)
         return dstChan == 5;
       if (isBundleInList(dstBundle, {WireBundle::South, WireBundle::North}))
         return true;
     }
     if (isBundleInList(srcBundle, {WireBundle::South, WireBundle::North})) {
-      if (isBundleInList(dstBundle, {WireBundle::DMA, WireBundle::Ctrl}))
+      if (isBundleInList(dstBundle, {WireBundle::DMA, WireBundle::TileControl}))
         return true;
       if (isBundleInList(dstBundle, {WireBundle::South, WireBundle::North}))
         return srcChan == dstChan;
@@ -602,18 +602,19 @@ bool AIE2TargetModel::isLegalTileConnection(int col, int row,
   }
   // Shimtile
   else if (isShimNOCorPLTile(col, row)) {
-    if (srcBundle == WireBundle::Ctrl)
-      return dstBundle != WireBundle::Ctrl;
+    if (srcBundle == WireBundle::TileControl)
+      return dstBundle != WireBundle::TileControl;
     if (isBundleInList(srcBundle, {WireBundle::FIFO, WireBundle::South}))
-      return isBundleInList(dstBundle, {WireBundle::Ctrl, WireBundle::FIFO,
-                                        WireBundle::South, WireBundle::West,
-                                        WireBundle::North, WireBundle::East});
+      return isBundleInList(dstBundle,
+                            {WireBundle::TileControl, WireBundle::FIFO,
+                             WireBundle::South, WireBundle::West,
+                             WireBundle::North, WireBundle::East});
     if (isBundleInList(srcBundle,
                        {WireBundle::West, WireBundle::North, WireBundle::East}))
       return (srcBundle == dstBundle)
                  ? (srcChan == dstChan)
                  : isBundleInList(dstBundle,
-                                  {WireBundle::Ctrl, WireBundle::FIFO,
+                                  {WireBundle::TileControl, WireBundle::FIFO,
                                    WireBundle::South, WireBundle::West,
                                    WireBundle::North, WireBundle::East});
     if (srcBundle == WireBundle::Trace) {
@@ -628,15 +629,16 @@ bool AIE2TargetModel::isLegalTileConnection(int col, int row,
     if (isBundleInList(srcBundle,
                        {WireBundle::DMA, WireBundle::FIFO, WireBundle::South,
                         WireBundle::West, WireBundle::North, WireBundle::East}))
-      if (isBundleInList(dstBundle,
-                         {WireBundle::Core, WireBundle::DMA, WireBundle::Ctrl,
-                          WireBundle::FIFO, WireBundle::South, WireBundle::West,
-                          WireBundle::North, WireBundle::East}))
+      if (isBundleInList(dstBundle, {WireBundle::Core, WireBundle::DMA,
+                                     WireBundle::TileControl, WireBundle::FIFO,
+                                     WireBundle::South, WireBundle::West,
+                                     WireBundle::North, WireBundle::East}))
         return (srcBundle == dstBundle) ? (srcChan == dstChan) : true;
     if (srcBundle == WireBundle::Core)
       return dstBundle != WireBundle::Core;
-    if (srcBundle == WireBundle::Ctrl)
-      return dstBundle != WireBundle::Ctrl && dstBundle != WireBundle::DMA;
+    if (srcBundle == WireBundle::TileControl)
+      return dstBundle != WireBundle::TileControl &&
+             dstBundle != WireBundle::DMA;
     if (srcBundle == WireBundle::Trace) {
       if (dstBundle == WireBundle::DMA)
         return dstChan == 0;

lib/Dialect/AIE/Transforms/AIEGenerateColumnControlOverlay.cpp

@@ -221,7 +221,7 @@ struct AIEGenerateColumnControlOverlayPass
 
         generatePacketFlowsForControl(
             builder, device, shimTile, AIE::WireBundle::South, tilesOnCol,
-            AIE::WireBundle::Ctrl, 0, tileIDMap, false);
+            AIE::WireBundle::TileControl, 0, tileIDMap, false);
       }
       if (clRouteShimDmaToTileCTRL) {
         // Get all tile ops on column col
@@ -234,7 +234,7 @@ struct AIEGenerateColumnControlOverlayPass
 
         generatePacketFlowsForControl(
             builder, device, shimTile, AIE::WireBundle::DMA, tilesOnCol,
-            AIE::WireBundle::Ctrl, 0, tileIDMap, true);
+            AIE::WireBundle::TileControl, 0, tileIDMap, true);
       }
     }
   }

lib/Dialect/AIE/Transforms/AIEPathFinder.cpp

@@ -195,10 +195,10 @@ void Pathfinder::initialize(int maxCol, int maxRow,
     SwitchboxConnect sb = {coords};
 
     const std::vector<WireBundle> bundles = {
-        WireBundle::Core,  WireBundle::DMA,  WireBundle::FIFO,
-        WireBundle::South, WireBundle::West, WireBundle::North,
-        WireBundle::East,  WireBundle::PLIO, WireBundle::NOC,
-        WireBundle::Trace, WireBundle::Ctrl};
+        WireBundle::Core,  WireBundle::DMA,        WireBundle::FIFO,
+        WireBundle::South, WireBundle::West,       WireBundle::North,
+        WireBundle::East,  WireBundle::PLIO,       WireBundle::NOC,
+        WireBundle::Trace, WireBundle::TileControl};
     for (WireBundle bundle : bundles) {
       // get all ports into current switchbox
       int channels =

lib/Targets/AIETargetXAIEV2.cpp

@@ -27,10 +27,8 @@ using namespace xilinx;
 using namespace xilinx::AIE;
 using namespace xilinx::AIEX;
 
-namespace xilinx::AIE {
-
 // This string is output at the top of the lowered C++ code.
-const char *xaie_cpp_file_header = R"code(
+static const char *xaie_cpp_file_header = R"code(
 // This file was auto-generated by aiecc.py --aie-generate-xaie.
 
 #ifndef MLIR_AIE_QUIET
@@ -69,13 +67,25 @@ static std::string tileLockStr(StringRef id, StringRef val) {
   return str;
 }
 
+// Translate mlir-aie WireBundle enum to string of aie-rt StrmSwPortType enum
+static std::string wireBundleToPortType(WireBundle bundle) {
+  switch (bundle) {
+  case WireBundle::PLIO:
+    return "PL";
+  case WireBundle::TileControl:
+    return "CTRL";
+  default:
+    return stringifyWireBundle(bundle).upper();
+  }
+}
+
 // FIXME: code bloat. this shouldn't really be a template, but need
 // a proper DMA-like interface
 // blockMap: A map that gives a unique bd ID assignment for every block.
 template <typename OpType>
-mlir::LogicalResult generateDMAConfig(OpType memOp, raw_ostream &output,
-                                      const AIETargetModel &targetModel,
-                                      DenseMap<Block *, int> blockMap) {
+static mlir::LogicalResult generateDMAConfig(OpType memOp, raw_ostream &output,
+                                             const AIETargetModel &targetModel,
+                                             DenseMap<Block *, int> blockMap) {
   StringRef enable = "XAIE_ENABLE";
   StringRef disable = "XAIE_DISABLE";
   StringRef deviceInstRef = "&(ctx->DevInst)"; // TODO
@@ -294,7 +304,8 @@ mlir::LogicalResult generateDMAConfig(OpType memOp, raw_ostream &output,
   return success();
 }
 
-mlir::LogicalResult AIETranslateToXAIEV2(ModuleOp module, raw_ostream &output) {
+mlir::LogicalResult xilinx::AIE::AIETranslateToXAIEV2(ModuleOp module,
+                                                      raw_ostream &output) {
   //  StringRef ctx   = "ctx";                     // TODO
   StringRef ctx_p = "aie_libxaie_ctx_t* ctx"; // TODO
   //  StringRef deviceInst = "ctx->DevInst";       // TODO
@@ -334,6 +345,8 @@ mlir::LogicalResult AIETranslateToXAIEV2(ModuleOp module, raw_ostream &output) {
   case AIEArch::AIE2p:
     device = AIE2p_device;
     break;
+  default:
+    return module.emitOpError("Unsupported aie.device");
   }
   output << "  ctx->AieConfigPtr.AieGen = " << device << ";\n";
   output << "  ctx->AieConfigPtr.BaseAddr = 0x20000000000;\n";
@@ -429,38 +442,6 @@ mlir::LogicalResult AIETranslateToXAIEV2(ModuleOp module, raw_ostream &output) {
   //---------------------------------------------------------------------------
   output << "int mlir_aie_configure_dmas(" << ctx_p << ") {\n";
 
-  // DMA configuration
-  // AieRC XAie_DmaDescInit(XAie_DevInst *DevInst, XAie_DmaDesc *DmaDesc,
-  // XAie_LocType Loc); AieRC XAie_DmaSetLock(XAie_DmaDesc *DmaDesc, XAie_Lock
-  // Acq, XAie_Lock Rel); AieRC XAie_DmaSetPkt(XAie_DmaDesc *DmaDesc,
-  // XAie_Packet Pkt); AieRC XAie_DmaSetOutofOrderBdId(XAie_DmaDesc *DmaDesc, u8
-  // OutofOrderBdId); AieRC XAie_DmaSetDoubleBuffer(XAie_DmaDesc *DmaDesc, u64
-  // Addr, XAie_Lock Acq, XAie_Lock Rel); AieRC XAie_DmaSetAddrLen(XAie_DmaDesc
-  // *DmaDesc, u64 Addr, u32 Len); AieRC XAie_DmaSetMultiDimAddr(XAie_DmaDesc
-  // *DmaDesc, XAie_DmaTensor *Tensor, u64 Addr, u32 Len); AieRC
-  // XAie_DmaEnableCompression(XAie_DmaDesc *DmaDesc); AieRC
-  // XAie_DmaSetNextBd(XAie_DmaDesc *DmaDesc, u8 NextBd, u8 EnableNextBd); AieRC
-  // XAie_DmaEnableBd(XAie_DmaDesc *DmaDesc); AieRC
-  // XAie_DmaDisableBd(XAie_DmaDesc *DmaDesc); AieRC XAie_DmaSetAxi(XAie_DmaDesc
-  // *DmaDesc, u8 Smid, u8 BurstLen, u8 Qos,u8 Cache, u8 Secure); AieRC
-  // XAie_DmaSetInterleaveEnable(XAie_DmaDesc *DmaDesc, u8 DoubleBuff, u8
-  // IntrleaveCount, u16 IntrleaveCurr); AieRC XAie_DmaWriteBd(XAie_DevInst
-  // *DevInst, XAie_DmaDesc *DmaDesc, XAie_LocType Loc, u8 BdNum);
-
-  // AieRC XAie_DmaChannelResetAll(XAie_DevInst *DevInst, XAie_LocType Loc,
-  // XAie_DmaChReset Reset); AieRC XAie_DmaChannelReset(XAie_DevInst *DevInst,
-  // XAie_LocType Loc, u8 ChNum, XAie_DmaDirection Dir, XAie_DmaChReset Reset);
-  // AieRC XAie_DmaChannelPauseStream(XAie_DevInst *DevInst, XAie_LocType Loc,
-  // u8 ChNum, XAie_DmaDirection Dir, u8 Pause); AieRC
-  // XAie_DmaChannelPauseMem(XAie_DevInst *DevInst, XAie_LocType Loc, u8 ChNum
-  // XAie_DmaDirection Dir, u8 Pause); AieRC XAie_DmaChannelConfig(XAie_DevInst
-  // *DevInst, XAie_DmaDesc *DmaDesc, XAie_LocType Loc, u8 ChNum,
-  // XAie_DmaDirection Dir, u8 RepeatCount, u8 EnTokenIssue, u8 ControllerId);
-  // AieRC XAie_DmaChannelPushBdToQueue(XAie_DevInst *DevInst, XAie_LocType Loc,
-  // u8 ChNum, XAie_DmaDirection Dir, u8 BdNum); AieRC
-  // XAie_DmaChannelEnable(XAie_DevInst *DevInst, XAie_LocType Loc, u8 ChNum,
-  // XAie_DmaDirection Dir); AieRC XAie_DmaChannelDisable(XAie_DevInst *DevInst,
-  // XAie_LocType Loc, u8 ChNum, XAie_DmaDirection Dir);
   for (auto memOp : targetOp.getOps<MemOp>()) {
     DenseMap<Block *, int> blockMap;
 
@@ -654,9 +635,9 @@ mlir::LogicalResult AIETranslateToXAIEV2(ModuleOp module, raw_ostream &output) {
     for (auto connectOp : b.getOps<ConnectOp>())
       output << "__mlir_aie_try(XAie_StrmConnCctEnable(" << deviceInstRef
              << ", " << tileLocStr("x", "y") << ", "
-             << stringifyWireBundle(connectOp.getSourceBundle()).upper() << ", "
+             << wireBundleToPortType(connectOp.getSourceBundle()) << ", "
              << connectOp.sourceIndex() << ", "
-             << stringifyWireBundle(connectOp.getDestBundle()).upper() << ", "
+             << wireBundleToPortType(connectOp.getDestBundle()) << ", "
              << connectOp.destIndex() << "));\n";
 
     for (auto connectOp : b.getOps<MasterSetOp>()) {
@@ -672,7 +653,7 @@ mlir::LogicalResult AIETranslateToXAIEV2(ModuleOp module, raw_ostream &output) {
 
       output << "__mlir_aie_try(XAie_StrmPktSwMstrPortEnable(" << deviceInstRef
              << ", " << tileLocStr("x", "y") << ", "
-             << stringifyWireBundle(connectOp.getDestBundle()).upper() << ", "
+             << wireBundleToPortType(connectOp.getDestBundle()) << ", "
              << connectOp.destIndex() << ", "
              << "/* drop_header */ "
              << (isdma ? "XAIE_SS_PKT_DROP_HEADER"
@@ -692,14 +673,14 @@ mlir::LogicalResult AIETranslateToXAIEV2(ModuleOp module, raw_ostream &output) {
         int msel = amselOp.getMselValue();
         output << "__mlir_aie_try(XAie_StrmPktSwSlavePortEnable("
                << deviceInstRef << ", " << tileLocStr("x", "y") << ", "
-               << stringifyWireBundle(connectOp.getSourceBundle()).upper()
-               << ", " << connectOp.sourceIndex() << "));\n";
+               << wireBundleToPortType(connectOp.getSourceBundle()) << ", "
+               << connectOp.sourceIndex() << "));\n";
 
         // TODO Need to better define packet id,type used here
         output << "__mlir_aie_try(XAie_StrmPktSwSlaveSlotEnable("
                << deviceInstRef << ", " << tileLocStr("x", "y") << ", "
-               << stringifyWireBundle(connectOp.getSourceBundle()).upper()
-               << ", " << connectOp.sourceIndex() << ", "
+               << wireBundleToPortType(connectOp.getSourceBundle()) << ", "
+               << connectOp.sourceIndex() << ", "
                << "/* slot */ " << slot << ", "
                << "/* packet */ " << packetStr(slotOp.valueInt(), /*type*/ 0)
                << ", "
@@ -740,22 +721,14 @@ mlir::LogicalResult AIETranslateToXAIEV2(ModuleOp module, raw_ostream &output) {
           connectOp.getDestBundle() == WireBundle::DMA) {
         if (connectOp.getSourceBundle() == WireBundle::North)
           // demux!
-          output
-              << "__mlir_aie_try(XAie_EnableAieToShimDmaStrmPort("
-              << deviceInstRef << ", " << tileLocStr("x", "y")
-              << ", "
-              //               <<
-              //               stringifyWireBundle(connectOp.sourceBundle()).upper()
-              << connectOp.sourceIndex() << "));\n";
+          output << "__mlir_aie_try(XAie_EnableAieToShimDmaStrmPort("
+                 << deviceInstRef << ", " << tileLocStr("x", "y") << ", "
+                 << connectOp.sourceIndex() << "));\n";
         else if (connectOp.getDestBundle() == WireBundle::North)
           // mux
-          output
-              << "__mlir_aie_try(XAie_EnableShimDmaToAieStrmPort("
-              << deviceInstRef << ", " << tileLocStr("x", "y")
-              << ", "
-              //               <<
-              //               stringifyWireBundle(connectOp.sourceBundle()).upper()
-              << connectOp.destIndex() << "));\n";
+          output << "__mlir_aie_try(XAie_EnableShimDmaToAieStrmPort("
+                 << deviceInstRef << ", " << tileLocStr("x", "y") << ", "
+                 << connectOp.destIndex() << "));\n";
       }
 
       else if (connectOp.getSourceBundle() == WireBundle::PLIO ||
@@ -784,9 +757,9 @@ mlir::LogicalResult AIETranslateToXAIEV2(ModuleOp module, raw_ostream &output) {
     for (auto connectOp : b.getOps<ConnectOp>())
       output << "__mlir_aie_try(XAie_StrmConnCctEnable(" << deviceInstRef
              << ", " << tileLocStr(col, 0) << ", "
-             << stringifyWireBundle(connectOp.getSourceBundle()).upper() << ", "
+             << wireBundleToPortType(connectOp.getSourceBundle()) << ", "
              << connectOp.sourceIndex() << ", "
-             << stringifyWireBundle(connectOp.getDestBundle()).upper() << ", "
+             << wireBundleToPortType(connectOp.getDestBundle()) << ", "
              << connectOp.destIndex() << "));\n";
   }
 
@@ -905,4 +878,3 @@ mlir::LogicalResult AIETranslateToXAIEV2(ModuleOp module, raw_ostream &output) {
 
   return success();
 }
-} // namespace xilinx::AIE

test/create-packet-flows/badpacket_flow.mlir

@@ -18,11 +18,11 @@ aie.device(npu1_1col) {
   %00 = aie.tile(0, 0)
   aie.packet_flow(28) {
     aie.packet_source<%00, DMA : 0>
-    aie.packet_dest<%02, Ctrl : 0>
+    aie.packet_dest<%02, TileControl : 0>
   }
   aie.packet_flow(29) {
     aie.packet_source<%00, DMA : 0>
-    aie.packet_dest<%03, Ctrl : 0>
+    aie.packet_dest<%03, TileControl : 0>
   }
   aie.packet_flow(26) {
     aie.packet_source<%00, DMA : 0>

test/create-packet-flows/packet_routing_priority_route.mlir

@@ -38,7 +38,7 @@ module @aie_module  {
 
   aie.packet_flow(0x2) {
     aie.packet_source<%t70, DMA : 0>
-    aie.packet_dest<%t72, Ctrl : 0>
+    aie.packet_dest<%t72, TileControl : 0>
   } {priority_route = true}
  }
 }

test/dialect/AIE/generate_column_control_overlay.mlir

@@ -18,32 +18,32 @@
 // CHECK: %[[tile_0_0:.*]] = aie.tile(0, 0)
 // CHECK: %[[tile_0_1:.*]] = aie.tile(0, 1)
 // CHECK: aie.packet_flow(15) {
-// CHECK:   aie.packet_source<%[[tile_0_0]], Ctrl : 0>
+// CHECK:   aie.packet_source<%[[tile_0_0]], TileControl : 0>
 // CHECK:   aie.packet_dest<%[[tile_0_0]], South : 0>
 // CHECK: }{{.*}}keep_pkt_header = true{{.*}}priority_route = true
 // TCTALLTILES-LABEL: module {
 // TCTALLTILES: %[[tile_0_0:.*]] = aie.tile(0, 0)
 // TCTALLTILES: %[[tile_0_1:.*]] = aie.tile(0, 1)
 // TCTALLTILES: aie.packet_flow(15) {
-// TCTALLTILES:   aie.packet_source<%[[tile_0_0]], Ctrl : 0>
+// TCTALLTILES:   aie.packet_source<%[[tile_0_0]], TileControl : 0>
 // TCTALLTILES:   aie.packet_dest<%[[tile_0_0]], South : 0>
 // TCTALLTILES: }{{.*}}keep_pkt_header = true{{.*}}priority_route = true
 // TCTALLTILES: aie.packet_flow(26) {
-// TCTALLTILES:   aie.packet_source<%[[tile_0_1]], Ctrl : 0>
+// TCTALLTILES:   aie.packet_source<%[[tile_0_1]], TileControl : 0>
 // TCTALLTILES:   aie.packet_dest<%[[tile_0_0]], South : 0>
 // TCTALLTILES: }{{.*}}keep_pkt_header = true{{.*}}priority_route = true
 // CTRLPKT-LABEL: module {
 // CTRLPKT: %[[tile_0_0:.*]] = aie.tile(0, 0)
 // CTRLPKT: %[[tile_0_1:.*]] = aie.tile(0, 1)
 // CTRLPKT: aie.packet_flow(15) {
 // CTRLPKT:   aie.packet_source<%[[tile_0_0]], DMA : 0>
-// CTRLPKT:   aie.packet_dest<%[[tile_0_0]], Ctrl : 0>
+// CTRLPKT:   aie.packet_dest<%[[tile_0_0]], TileControl : 0>
 // CTRLPKT: }
 // CTRLPKT: aie.shim_dma_allocation @ctrlpkt_col0_mm2s_chan0(MM2S, 0, 0)
 // CTRLPKT: memref.global "public" @ctrlpkt_col0_mm2s_chan0 : memref<2048xi32>
 // CTRLPKT: aie.packet_flow(26) {
 // CTRLPKT:   aie.packet_source<%[[tile_0_0]], DMA : 0>
-// CTRLPKT:   aie.packet_dest<%[[tile_0_1]], Ctrl : 0>
+// CTRLPKT:   aie.packet_dest<%[[tile_0_1]], TileControl : 0>
 // CTRLPKT: }
 
 aie.device(npu1_1col) {
@@ -61,11 +61,11 @@ aie.device(npu1_1col) {
 // CHECK: %[[tile_1_0:.*]] = aie.tile(1, 0)
 // CHECK: %[[tile_1_1:.*]] = aie.tile(1, 1)
 // CHECK: aie.packet_flow(15) {
-// CHECK:   aie.packet_source<%[[tile_0_0]], Ctrl : 0>
+// CHECK:   aie.packet_source<%[[tile_0_0]], TileControl : 0>
 // CHECK:   aie.packet_dest<%[[tile_0_0]], South : 0>
 // CHECK: }{{.*}}keep_pkt_header = true{{.*}}priority_route = true
 // CHECK: aie.packet_flow(15) {
-// CHECK:   aie.packet_source<%[[tile_1_0]], Ctrl : 0>
+// CHECK:   aie.packet_source<%[[tile_1_0]], TileControl : 0>
 // CHECK:   aie.packet_dest<%[[tile_1_0]], South : 0>
 // CHECK: }{{.*}}keep_pkt_header = true{{.*}}priority_route = true
 // TCTALLTILES-LABEL: module {
@@ -74,19 +74,19 @@ aie.device(npu1_1col) {
 // TCTALLTILES: %[[tile_1_0:.*]] = aie.tile(1, 0)
 // TCTALLTILES: %[[tile_1_1:.*]] = aie.tile(1, 1)
 // TCTALLTILES: aie.packet_flow(15) {
-// TCTALLTILES:   aie.packet_source<%[[tile_0_0]], Ctrl : 0>
+// TCTALLTILES:   aie.packet_source<%[[tile_0_0]], TileControl : 0>
 // TCTALLTILES:   aie.packet_dest<%[[tile_0_0]], South : 0>
 // TCTALLTILES: }{{.*}}keep_pkt_header = true{{.*}}priority_route = true
 // TCTALLTILES: aie.packet_flow(26) {
-// TCTALLTILES:   aie.packet_source<%[[tile_0_1]], Ctrl : 0>
+// TCTALLTILES:   aie.packet_source<%[[tile_0_1]], TileControl : 0>
 // TCTALLTILES:   aie.packet_dest<%[[tile_0_0]], South : 0>
 // TCTALLTILES: }{{.*}}keep_pkt_header = true{{.*}}priority_route = true
 // TCTALLTILES: aie.packet_flow(15) {
-// TCTALLTILES:   aie.packet_source<%[[tile_1_0]], Ctrl : 0>
+// TCTALLTILES:   aie.packet_source<%[[tile_1_0]], TileControl : 0>
 // TCTALLTILES:   aie.packet_dest<%[[tile_1_0]], South : 0>
 // TCTALLTILES: }{{.*}}keep_pkt_header = true{{.*}}priority_route = true
 // TCTALLTILES: aie.packet_flow(26) {
-// TCTALLTILES:   aie.packet_source<%[[tile_1_1]], Ctrl : 0>
+// TCTALLTILES:   aie.packet_source<%[[tile_1_1]], TileControl : 0>
 // TCTALLTILES:   aie.packet_dest<%[[tile_1_0]], South : 0>
 // TCTALLTILES: }{{.*}}keep_pkt_header = true{{.*}}priority_route = true
 // CTRLPKT-LABEL: module {
@@ -96,23 +96,23 @@ aie.device(npu1_1col) {
 // CTRLPKT: %[[tile_1_1:.*]] = aie.tile(1, 1)
 // CTRLPKT: aie.packet_flow(15) {
 // CTRLPKT:   aie.packet_source<%[[tile_0_0]], DMA : 0>
-// CTRLPKT:   aie.packet_dest<%[[tile_0_0]], Ctrl : 0>
+// CTRLPKT:   aie.packet_dest<%[[tile_0_0]], TileControl : 0>
 // CTRLPKT: }
 // CTRLPKT: aie.shim_dma_allocation @ctrlpkt_col0_mm2s_chan0(MM2S, 0, 0)
 // CTRLPKT: memref.global "public" @ctrlpkt_col0_mm2s_chan0 : memref<2048xi32>
 // CTRLPKT: aie.packet_flow(26) {
 // CTRLPKT:   aie.packet_source<%[[tile_0_0]], DMA : 0>
-// CTRLPKT:   aie.packet_dest<%[[tile_0_1]], Ctrl : 0>
+// CTRLPKT:   aie.packet_dest<%[[tile_0_1]], TileControl : 0>
 // CTRLPKT: }
 // CTRLPKT: aie.packet_flow(15) {
 // CTRLPKT:   aie.packet_source<%[[tile_1_0]], DMA : 0>
-// CTRLPKT:   aie.packet_dest<%[[tile_1_0]], Ctrl : 0>
+// CTRLPKT:   aie.packet_dest<%[[tile_1_0]], TileControl : 0>
 // CTRLPKT: }
 // CTRLPKT: aie.shim_dma_allocation @ctrlpkt_col1_mm2s_chan0(MM2S, 0, 1)
 // CTRLPKT: memref.global "public" @ctrlpkt_col1_mm2s_chan0 : memref<2048xi32>
 // CTRLPKT: aie.packet_flow(26) {
 // CTRLPKT:   aie.packet_source<%[[tile_1_0]], DMA : 0>
-// CTRLPKT:   aie.packet_dest<%[[tile_1_1]], Ctrl : 0>
+// CTRLPKT:   aie.packet_dest<%[[tile_1_1]], TileControl : 0>
 // CTRLPKT: }
 
 aie.device(npu1_2col) {
@@ -137,11 +137,11 @@ aie.device(npu1_2col) {
 // CHECK: %[[tile_1_0:.*]] = aie.tile(1, 0) {controller_id = #aie.packet_info<pkt_type = 0, pkt_id = 5>}
 // CHECK: %[[tile_1_1:.*]] = aie.tile(1, 1) {controller_id = #aie.packet_info<pkt_type = 0, pkt_id = 7>}
 // CHECK: aie.packet_flow(4) {
-// CHECK:   aie.packet_source<%[[tile_0_0]], Ctrl : 0>
+// CHECK:   aie.packet_source<%[[tile_0_0]], TileControl : 0>
 // CHECK:   aie.packet_dest<%[[tile_0_0]], South : 0>
 // CHECK: }{{.*}}keep_pkt_header = true{{.*}}priority_route = true
 // CHECK: aie.packet_flow(5) {
-// CHECK:   aie.packet_source<%[[tile_1_0]], Ctrl : 0>
+// CHECK:   aie.packet_source<%[[tile_1_0]], TileControl : 0>
 // CHECK:   aie.packet_dest<%[[tile_1_0]], South : 0>
 // CHECK: }{{.*}}keep_pkt_header = true{{.*}}priority_route = true
 // TCTALLTILES-LABEL: module {
@@ -154,35 +154,35 @@ aie.device(npu1_2col) {
 // TCTALLTILES: %[[tile_1_0:.*]] = aie.tile(1, 0) {controller_id = #aie.packet_info<pkt_type = 0, pkt_id = 5>}
 // TCTALLTILES: %[[tile_1_1:.*]] = aie.tile(1, 1) {controller_id = #aie.packet_info<pkt_type = 0, pkt_id = 7>}
 // TCTALLTILES: aie.packet_flow(4) {
-// TCTALLTILES:   aie.packet_source<%[[tile_0_0]], Ctrl : 0>
+// TCTALLTILES:   aie.packet_source<%[[tile_0_0]], TileControl : 0>
 // TCTALLTILES:   aie.packet_dest<%[[tile_0_0]], South : 0>
 // TCTALLTILES: }{{.*}}keep_pkt_header = true{{.*}}priority_route = true
 // TCTALLTILES: aie.packet_flow(3) {
-// TCTALLTILES:   aie.packet_source<%[[tile_0_1]], Ctrl : 0>
+// TCTALLTILES:   aie.packet_source<%[[tile_0_1]], TileControl : 0>
 // TCTALLTILES:   aie.packet_dest<%[[tile_0_0]], South : 0>
 // TCTALLTILES: }{{.*}}keep_pkt_header = true{{.*}}priority_route = true
 // TCTALLTILES: aie.packet_flow(5) {
-// TCTALLTILES:   aie.packet_source<%[[tile_0_2]], Ctrl : 0>
+// TCTALLTILES:   aie.packet_source<%[[tile_0_2]], TileControl : 0>
 // TCTALLTILES:   aie.packet_dest<%[[tile_0_0]], South : 0>
 // TCTALLTILES: }{{.*}}keep_pkt_header = true{{.*}}priority_route = true
 // TCTALLTILES: aie.packet_flow(1) {
-// TCTALLTILES:   aie.packet_source<%[[tile_0_3]], Ctrl : 0>
+// TCTALLTILES:   aie.packet_source<%[[tile_0_3]], TileControl : 0>
 // TCTALLTILES:   aie.packet_dest<%[[tile_0_0]], South : 0>
 // TCTALLTILES: }{{.*}}keep_pkt_header = true{{.*}}priority_route = true
 // TCTALLTILES: aie.packet_flow(6) {
-// TCTALLTILES:   aie.packet_source<%[[tile_0_4]], Ctrl : 0>
+// TCTALLTILES:   aie.packet_source<%[[tile_0_4]], TileControl : 0>
 // TCTALLTILES:   aie.packet_dest<%[[tile_0_0]], South : 0>
 // TCTALLTILES: }{{.*}}keep_pkt_header = true{{.*}}priority_route = true
 // TCTALLTILES: aie.packet_flow(2) {
-// TCTALLTILES:   aie.packet_source<%[[tile_0_5]], Ctrl : 0>
+// TCTALLTILES:   aie.packet_source<%[[tile_0_5]], TileControl : 0>
 // TCTALLTILES:   aie.packet_dest<%[[tile_0_0]], South : 0>
 // TCTALLTILES: }{{.*}}keep_pkt_header = true{{.*}}priority_route = true
 // TCTALLTILES: aie.packet_flow(5) {
-// TCTALLTILES:   aie.packet_source<%[[tile_1_0]], Ctrl : 0>
+// TCTALLTILES:   aie.packet_source<%[[tile_1_0]], TileControl : 0>
 // TCTALLTILES:   aie.packet_dest<%[[tile_1_0]], South : 0>
 // TCTALLTILES: }{{.*}}keep_pkt_header = true{{.*}}priority_route = true
 // TCTALLTILES: aie.packet_flow(7) {
-// TCTALLTILES:   aie.packet_source<%[[tile_1_1]], Ctrl : 0>
+// TCTALLTILES:   aie.packet_source<%[[tile_1_1]], TileControl : 0>
 // TCTALLTILES:   aie.packet_dest<%[[tile_1_0]], South : 0>
 // TCTALLTILES: }{{.*}}keep_pkt_header = true{{.*}}priority_route = true
 // CTRLPKT-LABEL: module {
@@ -196,41 +196,41 @@ aie.device(npu1_2col) {
 // CTRLPKT: %[[tile_1_1:.*]] = aie.tile(1, 1) {controller_id = #aie.packet_info<pkt_type = 0, pkt_id = 7>}
 // CTRLPKT: aie.packet_flow(4) {
 // CTRLPKT:   aie.packet_source<%[[tile_0_0]], DMA : 0>
-// CTRLPKT:   aie.packet_dest<%[[tile_0_0]], Ctrl : 0>
+// CTRLPKT:   aie.packet_dest<%[[tile_0_0]], TileControl : 0>
 // CTRLPKT: }
 // CTRLPKT: aie.shim_dma_allocation @ctrlpkt_col0_mm2s_chan0(MM2S, 0, 0)
 // CTRLPKT: memref.global "public" @ctrlpkt_col0_mm2s_chan0 : memref<2048xi32>
 // CTRLPKT: aie.packet_flow(3) {
 // CTRLPKT:   aie.packet_source<%[[tile_0_0]], DMA : 0>
-// CTRLPKT:   aie.packet_dest<%[[tile_0_1]], Ctrl : 0>
+// CTRLPKT:   aie.packet_dest<%[[tile_0_1]], TileControl : 0>
 // CTRLPKT: }
 // CTRLPKT: aie.packet_flow(5) {
 // CTRLPKT:   aie.packet_source<%[[tile_0_0]], DMA : 0>
-// CTRLPKT:   aie.packet_dest<%[[tile_0_2]], Ctrl : 0>
+// CTRLPKT:   aie.packet_dest<%[[tile_0_2]], TileControl : 0>
 // CTRLPKT: }
 // CTRLPKT: aie.packet_flow(1) {
 // CTRLPKT:   aie.packet_source<%[[tile_0_0]], DMA : 1>
-// CTRLPKT:   aie.packet_dest<%[[tile_0_3]], Ctrl : 0>
+// CTRLPKT:   aie.packet_dest<%[[tile_0_3]], TileControl : 0>
 // CTRLPKT: }
 // CTRLPKT: aie.shim_dma_allocation @ctrlpkt_col0_mm2s_chan1(MM2S, 1, 0)
 // CTRLPKT: memref.global "public" @ctrlpkt_col0_mm2s_chan1 : memref<2048xi32>
 // CTRLPKT: aie.packet_flow(6) {
 // CTRLPKT:   aie.packet_source<%[[tile_0_0]], DMA : 1>
-// CTRLPKT:   aie.packet_dest<%[[tile_0_4]], Ctrl : 0>
+// CTRLPKT:   aie.packet_dest<%[[tile_0_4]], TileControl : 0>
 // CTRLPKT: }
 // CTRLPKT: aie.packet_flow(2) {
 // CTRLPKT:   aie.packet_source<%[[tile_0_0]], DMA : 1>
-// CTRLPKT:   aie.packet_dest<%[[tile_0_5]], Ctrl : 0>
+// CTRLPKT:   aie.packet_dest<%[[tile_0_5]], TileControl : 0>
 // CTRLPKT: }
 // CTRLPKT: aie.packet_flow(5) {
 // CTRLPKT:   aie.packet_source<%[[tile_1_0]], DMA : 0>
-// CTRLPKT:   aie.packet_dest<%[[tile_1_0]], Ctrl : 0>
+// CTRLPKT:   aie.packet_dest<%[[tile_1_0]], TileControl : 0>
 // CTRLPKT: }
 // CTRLPKT: aie.shim_dma_allocation @ctrlpkt_col1_mm2s_chan0(MM2S, 0, 1)
 // CTRLPKT: memref.global "public" @ctrlpkt_col1_mm2s_chan0 : memref<2048xi32>
 // CTRLPKT: aie.packet_flow(7) {
 // CTRLPKT:   aie.packet_source<%[[tile_1_0]], DMA : 0>
-// CTRLPKT:   aie.packet_dest<%[[tile_1_1]], Ctrl : 0>
+// CTRLPKT:   aie.packet_dest<%[[tile_1_1]], TileControl : 0>
 // CTRLPKT: }
 
 aie.device(npu1_2col) {

test/dialect/AIE/switchbox-vc1902.mlir

@@ -22,8 +22,8 @@ module {
       aie.connect<North: 3, South: 3> // 4 southgoing connections
       aie.connect<West: 3, East: 3> // 4 eastgoing connections
       aie.connect<Trace: 0, South: 1>
-      aie.connect<Ctrl: 0, North: 2>
-      aie.connect<North: 2, Ctrl: 0>
+      aie.connect<TileControl: 0, North: 2>
+      aie.connect<North: 2, TileControl: 0>
     }
 
     %30 = aie.tile(3, 0) // Shim-NOC
@@ -91,8 +91,8 @@ module {
       aie.connect<East: 3, West: 3> // 4 westgoing connections
       aie.connect<North: 3, South: 3> // 4 southgoing connections
       aie.connect<West: 3, East: 3> // 4 eastgoing connections
-      aie.connect<Ctrl: 0, North: 1>
-      aie.connect<North: 2, Ctrl: 0>
+      aie.connect<TileControl: 0, North: 1>
+      aie.connect<North: 2, TileControl: 0>
     }
   }
 }

test/dialect/AIE/switchbox-ve2802.mlir

@@ -22,8 +22,8 @@ module {
       aie.connect<North: 3, South: 3> // 4 southgoing connections
       aie.connect<West: 3, East: 3> // 4 eastgoing connections
       aie.connect<Trace: 0, South: 1>
-      aie.connect<Ctrl: 0, North: 2>
-      aie.connect<North: 2, Ctrl: 0>
+      aie.connect<TileControl: 0, North: 2>
+      aie.connect<North: 2, TileControl: 0>
     }
 
     %30 = aie.tile(3, 0) // Shim-NOC
@@ -87,8 +87,8 @@ module {
       aie.connect<South: 5, North: 5> // 6 northgoing connections
       aie.connect<North: 3, South: 3> // 4 southgoing connections
       aie.connect<Trace: 0, South: 1>
-      aie.connect<Ctrl: 0, North: 2>
-      aie.connect<North: 2, Ctrl: 0>
+      aie.connect<TileControl: 0, North: 2>
+      aie.connect<North: 2, TileControl: 0>
     }
 
     %03 = aie.tile(1, 3) // core tile
@@ -101,8 +101,8 @@ module {
       aie.connect<East: 3, West: 3> // 4 westgoing connections
       aie.connect<North: 3, South: 3> // 4 southgoing connections
       aie.connect<West: 3, East: 3> // 4 eastgoing connections
-      aie.connect<Ctrl: 0, North: 2>
-      aie.connect<North: 2, Ctrl: 0>
+      aie.connect<TileControl: 0, North: 2>
+      aie.connect<North: 2, TileControl: 0>
     }
   }
 }

test/npu-xrt/add_one_ctrl_packet/aie.mlir

@@ -27,10 +27,10 @@ module {
 
     aie.packet_flow(0x1) {
       aie.packet_source<%tile_0_0, DMA : 0>
-      aie.packet_dest<%tile_0_2, Ctrl : 0>
+      aie.packet_dest<%tile_0_2, TileControl : 0>
     }
     aie.packet_flow(0x2) {
-      aie.packet_source<%tile_0_2, Ctrl : 0>
+      aie.packet_source<%tile_0_2, TileControl : 0>
       aie.packet_dest<%tile_0_0, DMA : 0>
     }
     aie.packet_flow(0x3) {

test/npu-xrt/add_one_ctrl_packet_4_cores/aie.mlir

@@ -60,19 +60,19 @@ module {
 
     aie.packet_flow(0x5) {
       aie.packet_source<%tile_0_0, DMA : 0>
-      aie.packet_dest<%tile_0_2, Ctrl : 0>
+      aie.packet_dest<%tile_0_2, TileControl : 0>
     }
     aie.packet_flow(0x6) {
       aie.packet_source<%tile_0_0, DMA : 0>
-      aie.packet_dest<%tile_0_3, Ctrl : 0>
+      aie.packet_dest<%tile_0_3, TileControl : 0>
     }
     aie.packet_flow(0x7) {
       aie.packet_source<%tile_0_0, DMA : 0>
-      aie.packet_dest<%tile_0_4, Ctrl : 0>
+      aie.packet_dest<%tile_0_4, TileControl : 0>
     }
     aie.packet_flow(0x8) {
       aie.packet_source<%tile_0_0, DMA : 1>
-      aie.packet_dest<%tile_0_5, Ctrl : 0>
+      aie.packet_dest<%tile_0_5, TileControl : 0>
     }
 
     aie.flow(%tile_0_2, DMA : 0, %tile_0_0, DMA : 1)

test/npu-xrt/add_one_ctrl_packet_col_overlay/test.cpp

@@ -211,4 +211,4 @@ int main(int argc, const char *argv[]) {
     std::cout << "\nfailed.\n\n";
     return 1;
   }
-}
+}

test/npu-xrt/memtile_dmas/writebd_tokens/aie.mlir

@@ -15,11 +15,11 @@ module {
     aie.flow(%tile_0_1, DMA : 0, %tile_0_0, DMA : 0)
 
     aie.packet_flow(0x1) {
-      aie.packet_source<%tile_0_1, "Ctrl" : 0>
+      aie.packet_source<%tile_0_1, "TileControl" : 0>
       aie.packet_dest<%tile_0_0, "South" : 0>
     }
     aie.packet_flow(0x2) {
-      aie.packet_source<%tile_0_0, "Ctrl" : 0>
+      aie.packet_source<%tile_0_0, "TileControl" : 0>
       aie.packet_dest<%tile_0_0, "South" : 0>
     }