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Verilog: create_module now returns verilog_module_sourcet #648

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Oct 25, 2024
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Verilog: create_module now returns verilog_module_sourcet #648

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13 changes: 9 additions & 4 deletions src/verilog/parser.y
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Original file line number Diff line number Diff line change
Expand Up @@ -614,6 +614,7 @@ description_brace:

description:
module_declaration
{ PARSER.parse_tree.add_item(stack_expr($1)); }
| udp_declaration
| interface_declaration
| program_declaration
Expand Down Expand Up @@ -672,7 +673,8 @@ module_ansi_header:
module_declaration:
module_nonansi_header module_item_brace TOK_ENDMODULE endmodule_identifier_opt
{
PARSER.parse_tree.create_module(
init($$);
stack_expr($$) = PARSER.parse_tree.create_module(
stack_expr($1).operands()[0],
stack_expr($1).operands()[1],
stack_expr($1).operands()[2],
Expand All @@ -685,7 +687,8 @@ module_declaration:
}
| module_ansi_header module_item_brace TOK_ENDMODULE endmodule_identifier_opt
{
PARSER.parse_tree.create_module(
init($$);
stack_expr($$) = PARSER.parse_tree.create_module(
stack_expr($1).operands()[0],
stack_expr($1).operands()[1],
stack_expr($1).operands()[2],
Expand All @@ -697,9 +700,11 @@ module_declaration:
pop_scope();
}
| TOK_EXTERN module_nonansi_header
/* ignored for now */
/* ignored for now */
{ init($$); }
| TOK_EXTERN module_ansi_header
/* ignored for now */
/* ignored for now */
{ init($$); }
;

module_keyword:
Expand Down
2 changes: 2 additions & 0 deletions src/verilog/verilog_language.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -83,6 +83,8 @@ bool verilog_languaget::parse(

parse_tree.swap(verilog_parser.parse_tree);

parse_tree.build_module_map();

return result;
}

Expand Down
7 changes: 2 additions & 5 deletions src/verilog/verilog_parse_tree.cpp
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Expand Up @@ -21,7 +21,7 @@ Function: verilog_parse_treet::create_module

\*******************************************************************/

void verilog_parse_treet::create_module(
exprt verilog_parse_treet::create_module(
irept &attributes,
irept &module_keyword,
exprt &name,
Expand All @@ -41,10 +41,7 @@ void verilog_parse_treet::create_module(
((const exprt &)module_keyword).source_location();
new_module.add(ID_module_items) = std::move(module_items);

auto &new_item = add_item(std::move(new_module));

// add to module map
module_map[name.id()] = &to_verilog_module_source(new_item);
return static_cast<exprt &>(static_cast<irept &>(new_module));
}

/*******************************************************************\
Expand Down
2 changes: 1 addition & 1 deletion src/verilog/verilog_parse_tree.h
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Expand Up @@ -48,7 +48,7 @@ class verilog_parse_treet
return module_map.count(name)!=0;
}

void create_module(
static exprt create_module(
irept &attributes,
irept &module_keyword,
exprt &name,
Expand Down
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