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Verilog: add KNOWBUG test for synthesis of continuous assignments to variables #729

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merged 1 commit into from
Sep 24, 2024

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@kroening kroening force-pushed the continuous_assignment_to_variable_systemverilog3 branch from c984c30 to 1d9a4cb Compare September 24, 2024 15:50
@kroening kroening marked this pull request as ready for review September 24, 2024 18:24
@tautschnig tautschnig merged commit d9e1046 into main Sep 24, 2024
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@tautschnig tautschnig deleted the continuous_assignment_to_variable_systemverilog3 branch September 24, 2024 18:31
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