Verilog: add KNOWBUG test for synthesis of continuous assignments to variables#729
Merged
tautschnig merged 1 commit intomainfrom Sep 24, 2024
Merged
Conversation
kroening
force-pushed
the
continuous_assignment_to_variable_systemverilog3
branch
from
c984c30 to
1d9a4cb
Compare
tautschnig
approved these changes
Sep 24, 2024
tautschnig
deleted the
continuous_assignment_to_variable_systemverilog3
branch
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
2 participants
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
No description provided.