Verilog: set type of implicit nets #750
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tautschnig
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| warning().source_location = expr.source_location(); | ||
| warning() << "implicit wire " << symbol->display_name() << eom; |
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Why does this yield a warning, or, rather: in what way should the input have been modified?
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Add "recommend declaring the net"?
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If this is covered by the standard (as the commit message suggests), why is such a recommendation warranted?
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1800 2017 6.10 allows implicit declarations of nets. The type of these nets is to be derived from the LHS of the assignment or the type of the port connection. The warning when a net is declared implicitly is dropped by default; it can be reactivated with --warn-implicit-nets.
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1800 2017 6.10 allows implicit declarations of nets. The type of these nets is to be derived from the LHS of the assignment or the type of the port connection.