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Verilog: set type of implicit nets #750

Merged
merged 1 commit into from
Oct 10, 2024
Merged

Verilog: set type of implicit nets #750

merged 1 commit into from
Oct 10, 2024

Commits on Oct 10, 2024

  1. Verilog: set type of implicit nets 

    1800 2017 6.10 allows implicit declarations of nets.  The type of these nets
is to be derived from the LHS of the assignment or the type of the port
connection.

The warning when a net is declared implicitly is dropped by default; it can
be reactivated with --warn-implicit-nets.
    @kroening
    kroening committed Oct 10, 2024
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