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Verilog: `$typename` #775

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tautschnig merged 1 commit into main from typename

Oct 17, 2024

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kroening commented Oct 17, 2024

This implements SystemVerilog's $typename system function.


          Verilog: $typename

66769ff

This implements SystemVerilog's $typename system function.

kroening added the Verilog label

kroening marked this pull request as ready for review

October 17, 2024 18:30

tautschnig approved these changes

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tautschnig merged commit ae1d74b into main

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tautschnig deleted the typename branch

October 17, 2024 20:19

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