CHIPS Alliance

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110 repositories

caliptra-mcu-sw
Public
Caliptra MCU Software
Rust
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Apache License 2.0
•15•17•24•8•Updated Aug 2, 2025Aug 2, 2025
firrtl-spec
Public
The specification for the FIRRTL language
TeX
•32•60•25•18•Updated Aug 2, 2025Aug 2, 2025
sv-tests
Public
Test suite designed to check compliance with the SystemVerilog standard.
rtl verilog systemverilog hdl compliance-testing symbiflow
SystemVerilog
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ISC License
•83•336•46•20•Updated Aug 2, 2025Aug 2, 2025
Caliptra
Public
Caliptra IP and firmware for integrated Root of Trust block
Apache License 2.0
•49•314•53•5•Updated Aug 1, 2025Aug 1, 2025
adams-bridge
Public
Post-Quantum Cryptography IP Core (Crystals-Dilithium)
cryptography digital-signature lattice pqc ml-dsa-87
SystemVerilog
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Apache License 2.0
•7•33•13•1•Updated Aug 1, 2025Aug 1, 2025
caliptra-sw
Public
Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test
Rust
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Apache License 2.0
•63•120•153•64•Updated Aug 1, 2025Aug 1, 2025
caliptra-rtl
Public
HW Design Collateral for Caliptra RoT IP
SystemVerilog
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Apache License 2.0
•58•103•88•13•Updated Aug 1, 2025Aug 1, 2025
verilator
Public
Verilator open-source SystemVerilog simulator and lint system
C++
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GNU Lesser General Public License v3.0
•686•39•0•0•Updated Aug 1, 2025Aug 1, 2025
Surelog
Public
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
parser linter preprocessor antlr verilog python-api systemverilog uvm elaboration vpi
C++
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Apache License 2.0
•76•403•46•0•Updated Aug 1, 2025Aug 1, 2025
caliptra-ss
Public
HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.
security rot ocp root-of-trust caliptra opencomputeproject
SystemVerilog
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Apache License 2.0
•21•25•48•6•Updated Aug 1, 2025Aug 1, 2025
t1
Public
Scala
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Apache License 2.0
•39•282•19•27•Updated Aug 1, 2025Aug 1, 2025
i3c-core
Public
SystemVerilog
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Apache License 2.0
•10•31•4•1•Updated Aug 1, 2025Aug 1, 2025
sv-tests-results
Public
Output of the sv-tests runs.
HTML
•6•7•0•0•Updated Jul 31, 2025Jul 31, 2025
caliptra-dpe
Public
High level module that implements DPE and defines high-level traits that are used to communicate with the crypto peripherals and PCRs
Rust
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Apache License 2.0
•26•17•16•8•Updated Jul 29, 2025Jul 29, 2025
chisel
Public
Chisel: A Modern Hardware Design Language
chip-generator chisel rtl chisel3 firrtl scala verilog
Scala
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Apache License 2.0
•633•4.4k•341•145•Updated Jul 29, 2025Jul 29, 2025
UHDM
Public
Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
vpi-api serialization listener systemverilog ieee-standard vpi-interface
C++
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Apache License 2.0
•43•224•14•0•Updated Jul 27, 2025Jul 27, 2025
verible
Public
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
productivity analysis style-linter language-server-protocol syntax-tree lexer yacc systemverilog hacktoberfest lsp-server
C++
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Other
•244•1.6k•527•23•Updated Jul 22, 2025Jul 22, 2025
Cores-VeeR-EL2
Public
VeeR EL2 Core
fpga processor riscv rtl risc-v open-source-hardware fusesoc verilator riscv32 western-digital
SystemVerilog
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Apache License 2.0
•88•292•24•1•Updated Jul 21, 2025Jul 21, 2025
tac
Public
CHIPS Alliance Technical Advisory Council
Apache License 2.0
•26•7•13•3•Updated Jul 16, 2025Jul 16, 2025
riscv-vector-tests
Public
Unit tests generator for RVV 1.0
generator spike riscv testsuite rvv
Go
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Apache License 2.0
•30•89•10•1•Updated Jul 15, 2025Jul 15, 2025
homebrew-verible
Public
Ruby
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Apache License 2.0
•10•21•0•0•Updated Jul 14, 2025Jul 14, 2025
chips-alliance-website
Public
SCSS
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MIT License
•6•4•8•8•Updated Jul 11, 2025Jul 11, 2025
caliptra-cov
Public
0•0•0•0•Updated Jul 3, 2025Jul 3, 2025
firtool-resolver
Public
Shell
•2•6•0•1•Updated Jul 1, 2025Jul 1, 2025
caliptra-tools
Public
Apache License 2.0
•0•0•0•0•Updated Jun 13, 2025Jun 13, 2025
rvdecoderdb
Public
The Scala parser to parse riscv/riscv-opcodes generate
Nix
•9•21•1•1•Updated Jun 13, 2025Jun 13, 2025
VeeR-EL2-tock-example
Public
How to run a Tock app on VeeR EL2 in simulation
C
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Apache License 2.0
•1•2•0•0•Updated Jun 12, 2025Jun 12, 2025
synlig-logs
Public
Helper repo used in Synligs CI
SystemVerilog
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Apache License 2.0
•1•1•0•0•Updated Jun 12, 2025Jun 12, 2025
omnixtend
Public archive
OmniXtend cache coherence protocol
TeX
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Apache License 2.0
•15•82•1•0•Updated Jun 10, 2025Jun 10, 2025
espresso
Public
C
•17•40•6•1•Updated Jun 8, 2025Jun 8, 2025