Verilog: add KNOWBUG test for synthesis of continuous assignments to variables #2485
Triggered via pull request
September 24, 2024 15:44
kroening
Status
Failure
Total duration
15m 12s
Artifacts
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pull-request-checks.yaml
on: pull_request
check-ubuntu-20_04-make-clang
1m 19s
check-ubuntu-20_04-make-gcc
1m 6s
CentOS 8
57s
check-macos-14-make-clang
1m 25s
Emscripten build
38s
check-vs-2022-make-build-and-test
14m 59s
benchmarking
0s
Annotations
4 errors
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CentOS 8
Process completed with exit code 2.
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check-ubuntu-20_04-make-gcc
Process completed with exit code 2.
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check-ubuntu-20_04-make-clang
Process completed with exit code 2.
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check-macos-14-make-clang
Process completed with exit code 2.
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