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Ruige Lee edited this page Jan 27, 2021 · 3 revisions

D Flip-Flop with Enable

Parameter

Name Description
DW data width
rstValue reset value

Port

Name Direction Width Description
dnxt Input DW Input of Flip-Flop
qout Output DW Output of Flip-Flop
en Input 1 Allow data update in next clock cycle, Active High
CLK Input 1 Clock drives the Flip-Flop
RSTn Input 1 Asynchronous reset of Flip-Flop. Active Low

To allow blocking update, D Flip-Flop with Enable add an enable port, based on D-FF.

DFFen

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