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pc generate
Ruige Lee edited this page Jan 26, 2021
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In this stage, the next fetch address is generated.
- By default, the next address is the
+8
of the previous address, which is 64bits align, and the instruction fetch stage fetches 64bits instruction every time. - When there is a mispredict or
fence_i
retire orjalr
resolved, the address will update frombranch predict unit
, which can be not 64bits align - when there is an expectation flush, the address will update from
commit
, which can be not 64bits align.