Sync FIFO
| Name | Description |
|---|---|
| DW | data width |
| AW | Address Width of FIFO |
| Name | Direction | Width | Description |
|---|---|---|---|
| fifo_pop | Input | 1 | Pop one data from the FIFO |
| fifo_push | Input | 1 | Push one data into the FIFO |
| data_push | Input | DW | The data that push into the FIFO |
| data_pop | Output | DW | The last data in the FIFO, which will be pop next |
| fifo_empty | Output | 1 | The signal shows the FIFO is Empty
|
| fifo_full | Output | 1 | The signal shows the FIFO is Full
|
| read_addr | Output | AW+1 | Extend signal which is used for Half/Quarter Full/Empty detection |
| write_addr | Output | AW+1 | Extend signal which is used for Half/Quarter Full/Empty detection |
| flush | Input | 1 | synchronous reset of the FIFO, Active High |
| CLK | Input | 1 | Input clock for timing element |
| RSTn | Input | 1 | Asynchronous reset of the FIFO. Active Low |
Synchronize FIFO is the basic element of timing logic.
