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Ruige Lee edited this page Jan 26, 2021 · 2 revisions

instruction-decode

Instruction decoder is just a lookup table implemented in combination logic, which fan out 32-bits (or 16 bits) instructions into micro-op, imm, rs1, rs2, rd0, and so on.

The RCV checked in pre-decode will decide which decoder is used, 16bits or 32bits.

After decoder, there is an instruction FIFO before the dispatch-stage, which directly decouples the frontend and backend.

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pc generate

instruction fetch

instruction queue

instruction decode

instruction FIFO

dispatch

issue

execute

writeback

commit

out of order implementation

Parity memory

inner bus

FPGA Implementation

Basic Element

D Flip-Flop

D Flip-Flop with enable

RS Flip-Flop

Sync FIFO

Bypass FIFO

Ring Stack

SRAM

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