issue

issue

There are 3 kinds of issue implementation, directly in-order, directly out-of-order, in-order-outside-out-of-order-inside.

directly in-order

• The bru and csr are not quite necessary to execute out-of-order.
  • Bru will not generate an rd result. So it will not cause a RAW data hazard to the following instruction. When the branch prediction is correct, the result is produced in branch-predict-unit. If it is executed out-of-order, a much complex module should be implemented to reorder the pipeline flush. It's a low-profit design.
  • csr execution can not be canceled even if it has not been committed. As a result, csr should not be executed out-of-order.

directly out-of-order

alu, mul are implemented in out-of-order style issue. These kinds of issues will check all the valid buffer. If the RAW data hazard is resolved, the execution information will be sent to the execution unit.

in-order-outside-out-of-order-inside

• The lsu may implementation in this way in the following version, to improve the performance.
• Memory access is the bottleneck of process performance.
  • For memory writing, it can not be revoked. it can only be executed after the previous instructions are committed. As a result, it's issued in order.
  • For memory reading, RAR is not a data Hazard. It's issued out of order.
  • For the sequence between memory writing and reading, RAWmay happen. It necessary to check whether there is the same address will be written before a reading transmission.
  • For fence, part of instructions must be executed in order.

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issue block

Some situations may block the issue.

1. csr block csr execution can not be canceled even if it has not been committed. The operation of the csr register will cause effort once it has been done. As a result, csr instruction will not be issued, until the previous instruction has been committed.
2. lsu block Store memory execution can not be canceled even if it has not been committed. Also fence instruction will alter the execution order.