out of order implementation
There is an out-of-order black box consisted of issue-stage, execute-stage, and writeback-stage. All instructions inputted will be processed out of order，if observed outside. In the black box, the same instructions may be processed in order with the constraint. Dispatch and Commit are the entry and exit of the out of order implementation. There is a reorder FIFO used to re-order the instruction.
Each integer register has 4 rename depth in the current version. 128 register files are created to store the data. 32 rename-active-pointers will indicate the indexes of the active registers observing before the out-of-order black box. They are the real rs1 and rs2 will be dispatch. A new and free rd index will be malloced, and the rename-active-pointer will be updated. In this way, all WAW and WAR data hazards are resolved. The dispatch stage will be stalled if no free rd index available and a rename-log will indicate that.
Instruction info will be dispatched in the dispatch-stage one by one, meanwhile, the renamed rd index will be pushed into a reorder FIFO. A writeback log will indicate whether an instruction is finished its execution by looking up the writeback log. Once the first rd in reorder FIFO is written back, it can be committed, and its last rename-log and writeback-log can be release. Once data is written back, a RAW data hazard is resolved and the operands will be read out in issue-state. The instruction will be executed in the next cycle if the execution units are ready. 32 Architecture Register Pointers are used to indicate the active register observing after out-of-order black box. The registers they pointing to are the real architecture registers. Once a flush occurs, all following instructions will be canceled and the rename-active-pointers, rename-log, writeback-log can be rebuilt by Architecture Register Pointers.
- only the rd sequence is needed to reorder. No same rd will appear in the reorder Fifo for the dispatch-state will stall if that happened. But additional information will push into reorder FIFO for other usages.
- If one writeback log is reset, the data is abandoned. Don't worry about reading operands. The stages before the out-of-order black box only observe the rename-active-pointers.
- Both the rename-log and writeback-log will not set and reset one bit at the same time in one cycle.
