dispatch
Decoupled from the frontend, the dispatch stage is the first stage of the backend. The decoded information is pop out from instruction FIFO. The rs1 and rs2 are looked up from the rename table according to the rename active pointer, and the real indexes of rs1, rs2 will be dispatched. The rd0 will be malloc from the rename buffer if there is a free position, or the dispatch-stage will be stalled. All WAR and WAW will be resolved in this stage.
According to the execution unit and instruction, the information will be dispatched to different FIFO or parallel buffer belongs to the execution unit.
rename is a way to resolve Name Dependences and Fatal Data Hazards. Statically, the compiler may finish part of rename operation. however, the registers defined by ISA is limited. Also, there is uncertainty when the processor operates. Renaming dynamically is necessary to implement.
In this version, each register is expanded to 4. That is 128 registers, 4 rename depth. The indexes of the register are extended from 5bits to 7bits. [4:0] presents the register index ISA defined. [6:5] presents the depths of register. Every time when instruction with return result (rd) is dispatched, space will be malloc from the rename buffer, active pointer will be pointed to that depth, and the register will be marked as in used. WAW and WAR are resolved in this way for there no previous instruction is reading or writing that register, when malloc success. The active pointer pointers to are where rs1, rs2 read operator.
